How to force the DC to generation TIEHI and TIELO

[yanzixuan]

How to force the DC to generate TIEHI and TIELO

Hi All, I'm working on a project and I encountered a problem. After systhesis, I check the gate-netlist and found that: some ports of sub-block are assign to be 1'b0, 1'b1. But in normal condition, it should be connected to TIEHI and TIELO block for the concern of ESD.
after removing the dont_use attribution form TIEHI and TIELO lib cells and using "set_drive_power_rail_tie", the result is the same!
So can anybody know how to fix this problem?
Thanks! bow

 

[yx.yang]

Re: How to force the DC to generate TIEHI and TIELO

Hi, Please see the following link for detail: https://www.edaboard.com/threads/89282/
I think the following will work:
set verilogout_no_tri true
set verilogout_equation false

current_design $top_design_name
set_fix_multiple_port_nets -all -buffer_constants