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No DC will not do this.
This needs to be done by the user. He has to estimate the target skew or uncertainty and give this to the tool.
Normally we go with 10-15 percent clock period as uncertainty. But this depends on the design also.
When you indicate CTS, did you mean for Clock tree Synthesis? In general the tool used the sdc to indicate where is(are) the clock source(s), and analyze the current clock tree to generate the clock tree constrain (in Cadence for example).
is it what you mean?
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