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Recent content by xuebi

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    salaries for embedded engineer

    salary for engineer in europe ------------------------------------ Now I'm applying for the IMEC in Belgium and terrified of what you said.:cry: After 55~60% tax and insurance deducted from the salary and life expediture, how much can I save for a month?:cry::cry::cry: Added after 6...
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    Need help on LNA topology

    Thanks! Sreechoudhary. Can you explain the three methods above a little more detailed?
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    Questions about LNA output design

    Generally speaking, the input impedance of the next stage is very high, so I can not check the power gain or S21 of the previous stage (LNA). I can just check the voltage gain of the LNA. Then how can I design the output network of the LNA? By the way, VHF band is for DAB or DMB applications.
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    Problems about LNA output design

    Thank you very much. If I want to include the next stage's input impendance, and L should resonate with the whole C , how can I set the output port using SpectreRF for simulation?
  5. X

    Problems about LNA output design

    Now I'm designing the output part of LNA and I found little literature focused the output design of LNA. The following are my questions: 1) The LNA will be connected to the next stage. How to include the next stage input impedance when I simulate LNA using SpectreRF? 2) I use the shunt peaking...
  6. X

    Questions about LNA output design

    Now I'm designing the output part of LNA and I found little literature focused the output design of LNA. The following are my questions: 1) The LNA will be connected to the next stage. How to include the next stage input impedance when I simulate LNA using SpectreRF? 2) I use the shunt peaking...
  7. X

    Need help on LNA topology

    Now I need design a LNA with its main specifications as following. BW: 174-245MHz, Gain: 20dB, NF: 2dB 0.18 CMOS process. It is a wideband LNA (Bandwidth~33%). The cascode architecture with source inductive degeneration is just suitable for narrowband. Moreover, the degeneration indutor...
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    Can anyone recommend me some proper LNA topology?

    Now I need design a LNA with its main specifications as following. BW: 174-245MHz, Gain: 20dB, NF: 2dB 0.18 CMOS process. It is a wideband LNA (Bandwidth~33%). The cascode architecture with source inductive degeneration is just suitable for narrowband. Moreover, the degeneration indutor will...
  9. X

    how to calculate ratio fo cmos transistors

    Re: CMOS Layout Questions There are still my questions without answers. Cheer up!
  10. X

    Looking for documents on how to design a RF VGA

    Re: How to design a RF VGA Now I am also focusing the design of VGLNA or LNA+VGA.
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    How can I begin my LNA design?

    This classical paper may be difficult for beginners to understand. What's more, I found a lot of knowledge about analog circuit is necessary for RFIC design.
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    Beginner - Layout techniques

    Where can I find this book? Thanks. IC Mask Design: Essential Layout Techniques by Christopher Saint, Judy Saint
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    How can I begin my LNA design?

    The project I am doing now is CMOS LNA, which is a little different from the traditional microwave LNA design. For example, I have to decide the size of the mos transistor. So I think it may be better if I can find a detailed design example. however, most textbooks just cover a lot of similar...

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