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Code coverage using GCOV
Hi Friends,
I am trying to find the coverage data of a header file used in a tool. The header file is basically a systemc ".h" file and it has been integrated with the tool. I have written tons of testcases to test all the functionalities defined in the said header...
Re: CMOS question?
130, 90, 60, 45 nm are technology nodes. It does of course mean the channel length of the transistor. But to say that, in a given technology, e.g. 90 nm, channel length varies from 70 to 100 nm from vendor to vendor and that is what makes one product better than the other in...
Re: tcl or perl
so many people so many words.........
for backend of course you need both Tcl and Perl. But for beginners, writing scripts for using tool is more important where Tcl is the best and all tools support Tcl. You can learn perl as you gain further experience and start doing...
Re: TCL
you can do google for some very good tcl tutorials for beginners.
There is a book called "Tcl and the Tk Toolkit" by John K. Ousterhout. I find this book very good for tcl.
Thanks Frank,
Thanks for your reply.
Others please refer Verilog HDL LRM (8.6.6 Intra-Assignment Timing Controls)
Frank, As you told that this is a synthesizable construct, can you please let me know which synthesis tool gives the intended netlist. Because I am not sure which tool can do...
synthesizable verilog construct
Thanks frank for your promt reply. But my code does not have any syntex error. I deliberately put @(negedge clk) after begin to control the event. This is valid syntax and passes with ncverilog simulation. Your solution is a very common flop architecture.
So my...
xilinx vhdl for loop
Well to append to the comment from echo47 "the master" :D , for loops with variable range are not synthesizable. For loops can only be used in a design with constant range of iteration :D
it looks like we are improving our vocab rather than our verilog :D
Anyways, I would love to add a few more word :|
Perseverance, determination, grit, insistence, resolution, diligence, resolve, drive, purpose, tenacity, dedication, obstinacy, devotion, tirelessness, endurance, steadfastness...
This looks a bit tricky.... we need to store previous values for counter. However this can also be done if combinational loops are used. Muxes are also combinational blocks and using muxes we can design counters. (Muxes having feedback loop).
Give it a thought. It should not be that difficult :D
Hey Friends,
I sincerely need your advice for my career options.
I am from india. I have done Bachelors in Electronics and Communication Engg. and a short term post graduate course in VLSI Design. I have good understanding of Digital Design, VHDL, Verilog and SystemC. I have also worked asFPGA...
You should be little more specific as to what do you want to implement.... Some of the telecom designs (partially) may be purely digital and you may use VHDL, but majority of them deals with Mixed Signals and VHDL-AMS is the best option to go for. :)
Hi Friends,
so much has already been said and discussed about LVDS in this board, I still need your help as I am deeling with LVDS first time and need your help.
I have an LVDS out put with one pair of data lines and one pair of clock lines. I have to implement an LVDS receiver in an Spartan3E...
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