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gated clock mux
I need synthesis a project with some gate or mux clock,
for example:
clk1 = clk1_en & clk_tx;
//clk_en1 comes from other clock domain: clk_pci
clk2 = state? clk_pci : clk_rx;
how set constraint ?
i try use set_case_analysis
or create_generated_clock, but not set right.
thanks
verilog range bounds are not constants
Verilog Assignment Rule:
part select must constant,
but bit select no limit in procedure assign:
so can use another method,
for(ii = 0;ii<8;ii=ii+1)
if (ii == addr_i)
for(jj = 0;jj<`w;jj=jj+1)
cast[ii*`w+jj] = data_i[jj];
else
for(jj = 0;jj<`w;jj=jj+1)...
range must be bounded by constant expressions
[...]
u can try other ways
use shift
cast = data_i << addr_i * 'w;
:it cant asign 'bZ
or use mem
reg [`w-1:0] cast [2:0]
for () cast[index] = `w'bz;
cast[addr_i] = data_i;
:it not fit function
pad, timing, function???
I think the important in RTL simulation is logic verification. Without the accurate model, the timing check is rough.
Also PAD timing need be considered in synthesis constrain, i.e. input_delay...
In final we check function and timing in simulation with SDF files...
fsdbdumpoff
from modesim user manual
-->
A VCD file from source to output
The following example shows the VHDL source, a set of simulator commands, and the resulting VCD output.
VHDL source code
The design is a simple shifter device represented by the following VHDL source code:
library IEEE...
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