xigu
Newbie level 5
gated clock mux
I need synthesis a project with some gate or mux clock,
for example:
clk1 = clk1_en & clk_tx;
//clk_en1 comes from other clock domain: clk_pci
clk2 = state? clk_pci : clk_rx;
how set constraint ?
i try use set_case_analysis
or create_generated_clock, but not set right.
thanks
I need synthesis a project with some gate or mux clock,
for example:
clk1 = clk1_en & clk_tx;
//clk_en1 comes from other clock domain: clk_pci
clk2 = state? clk_pci : clk_rx;
how set constraint ?
i try use set_case_analysis
or create_generated_clock, but not set right.
thanks