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Thanks for the reply!
Yes, I meant a flipflop in std cell library from foundry. Is there a common sense that which one (reset, !reset) consume more power?
Hi
I am a digital guy. When I am testing our chip in the lab. I found a weird thing
The chip is just power up, the most up stream block is output constant signal by default. We didn't do any configuration at all.
The weird thing is when I apply a global reset to digital core (hold reset to be...
I wrote a verilog module in RTL and use it to abstract high level clock gating function. I want to replace it to a ICG cell in synthesis in order to ease DFT and PR flow. But when I tried with Magma, the tool complain 'no delay node found, won't do any clockgating'. Anything do I miss or any...
I have been a ASIC (digital) design engineer for 6 years and before that I already had a MSEE degree. Now I am looking for a good program which can help me go further in IC industry such as to be a manager or a fellow designer. Do you have any idea?
Part time PhD or industry sponsored research...
Good idea!
That is for VHDL. Unfortunately, we don't have similar way in verilog. So currently I am doing is using PWM code to simulate the analog input. We all know that PWM code is able to describe a multi level value by using different pulse width. Obviously, I wrote the behavior which can...
Hi
I want to model a ADC in verilog and use it in digital simulation. My purpose is to make this behavior the same interface as the true analog one and use it in a digital SOC environment. Write some testbench to test its connection.
My problem is how to model the analog input because it is...
Re: Backend & analog
digital backend is working with always standard library from fab and don't need to care about how the standard cell is working internally. analog design have to look into the detail circuit down to MOS tube
For example, design standard cell is a analog job and use these...
Here is some suggestions I can think of
1. check if it is multi-driven net
2. check if the driving flop don't have a reset in start up
3. check if there is timing violations occur if you are doing post-sim with annotated timing information
4. if there is unconnect interface signal
Thanks to kishore2k4 and avimit
Yes, to look for a industry base part-time Ph.D is really a good idea. And it is also fit for me because I am more research qualify instead of management ability.
Do you guys have any more detail information from any IC company which is sponsoring a good program...
I have been a ASIC (digital) design engineer for 6 years and before that I already had a MSEE degree. Now I am looking for a good program which can help me go further in IC industry such as to be a manager or a fellow designer. Do you have any idea?
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