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Re: Verification methodology of motion estimation in H.264/A
Thank you for your answer.
I hope this way is good enough for verification, even it is quite difficult.
Win2Y
Re: Verification methodology of motion estimation in H.264/A
I used Verilog for RTL code. Motion estimation that I coded includes two parts: integer ME almost similar to JM reference software, and the other is fractional ME with new algorithm. However I want to make sure that RTL code with its...
Hi;
I am currently doing Motion estimation (ME) in H.264/AVC. My question is about verification methodology of motion estimation in H.264/AVC. Who has some experiences in this please help me? Could anyone interested in discuss together?
Any suggestion is welcome. Many thanks
Win3Y
Something misunderstood here. I wanna output signal to be delayed by clock. But your way just takes input at posedge clk by some clockcycles, but does not delay it.
Anyway, thank you for reply.
W3Y
Hi everybody;
I wanna make some control signals delayed 10 or more than 10 clock cycle. I just know the way like this:
reg [Nbit - 1:0] control_1_delay,control_2_delay,control_3_delay...control_10_delay;
always@(posedge CLK ore negedge nRESET)
if (!nRESET)
begin...
Hi everybody;
Is there any way to design a comparator N-bit with lowest cost?
The comparator I made as following:
input [N - 1:0] INP0, INP1;
output [N - 1:0] MIN;
assign MIN = (INP0 < INP1)? INP0:INP1;
I wish to make another comparator that occupies smaller hardware cost.
Thanks.
W3Y.
Hi everybody;
I need the solution for this problem:
Originally, I used 3 block RAMs (same content) with 3 separate Address reading signals.
For saving reason, I just have only one block RAM, so what the solution for this problem in case budget cycle is limited (timing constrained). If it is...
I mean that considering on BackEnd Engineering. If statement and assignment combinational logic, which one has more advantage. For example, comparing between them on the aspect of number of gate counts it may occupy and the delay it may have.
Thank you
W3Y
Some given posts are really interesting. Thank you very much.
To ljxp..: You are absolutely right ! I am that Back-End guy :D
Is there anyone here who did successfully with [1023:0] bus wide ?
W3Y
Thank you for your suggestion.
But I am still wondering whether my design has problem in such a big wire.
Does It cause error? And even not working correctly?
Win3Y
Hi Everybody;
I am going to fabricate my design using DC, Prime Time and Astro.
But I am wondering there is any problem in the design with a lot of wires while implementing Back-End work? Is there anyone had experience with this?
My design has 3 modules connected each other by some wires...
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