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Recent content by weng

  1. W

    logic to detect 1 bit (only 1 bit) High in a bus

    I need to have a logic to detect ONLY 1 bit high in a bus. For example: a bus signal Y[3:0]. output OUT High only if Y == 0001 or Y == 0010 or Y == 0100 or Y == 1000. What is the best way to code it in Verilog? In terms of min gate transition?
  2. W

    Can Huffman ECC detect 2 bits error ?

    Hi, Anyone know about the Huffman ECC code? Can Huffman ECC detect 2 bits error and how? Thanks.
  3. W

    How to add constraint to a wire?

    I tried to add constraint to a wire of my module. However, I always get "Warning: Can't find objects matching" How can I add constarint on a wire?
  4. W

    Symmid Corp, Malaysia

    symmid Hi, Anyone knows about Symmid Corp. from Malaysia?
  5. W

    How to design a SoC and where to find design examples?

    Re: how to design a soc? What is the difference between ASIC and FPGA?
  6. W

    How to initialize an array structure in verilog?

    verilog array initial How about if I only want to initialize one of the bit of mem? For example, I want to initialize the bit 0 of all mem array to 0?
  7. W

    How to initialize an array structure in verilog?

    verilog memory initialization Is this correct? Looks like you actually treat mem as a single bit signal, not a bus signal.
  8. W

    diff b/w latchs and flipflop

    flip-flop passes the input when clock triggers (positive edge or negative edge) latch passes the input when clock High (or Low)
  9. W

    What is the difference between reg and wire?

    Re: reg & wire How about in terms of synthesis? What will a reg type or a wire type looks like when synthesize? What are the difference?
  10. W

    What is the difference between reg and wire?

    reg & wire Hi, What is the difference between reg and wire? When should we use reg and when should we use wire?
  11. W

    what is the difference between #1 a<=b and a<=#1 b

    I am sorry that I didn't make my question clear. What I wanted to ask is whether these blocking and nonblocking assignments with delays reflect the actual circuit. How do the delays in both assignments synthesize to circuit?
  12. W

    Which gate has more delay: NAND or NOR?

    Re: Nand or NOR Delay Hi, When you say the NMOS and PMOS, you are refering to the peripheral circuits around the flash core array (eg sense amplifiers) but not the flash core array itself. Am I right?
  13. W

    use of parameters in verilog

    what is the difference between parameter and define?
  14. W

    What does Code Coverage mean ?

    Hi, I am talking about functional coverage, not code coverage. For code coverage, we check every line of the codes. But for functional coverage, we check the codes by testing all possible functions of the code(device). Functional coverage is higher level than code coverage. Am I right?
  15. W

    verilog code difference

    The first case is ok. a is assigned to b and at the same time b is assigned to a. That means a and b could have difference values depands on the initial values. For the second case, value of b is assigned to a and b wont change...
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