How to add constraint to a wire?

[weng]

I tried to add constraint to a wire of my module. However, I always get "Warning: Can't find objects matching"

How can I add constarint on a wire?

 

[rjainv]

what constraint is this ? Can you paste the exact command ?

 

[shiv_emf]

constraint on wire
wht do u mean ??/
is it @synthesis stage????
is it timing constraint or anything NEW ?????

 

[asicengineer1]

I'm guessing you are talking about a wire data type in verilog.

if it is so, my suggestion would be to constrain it as a combinational logic. i've heard that virtual clocks can be used to constrain combinational logic.

 

[shiv_emf]

YEah virtual clocks can be used to constrain combo logic ......
how shud I constrain it as COMBINATIONAL logic???
U mean placing all combo in one module???

 

[asicengineer1]

i'm not sure i follow. my understanding is, we use a virtual clock and use that to specify the delay values. i think we specify set_max_delay and set_min_delay.

 

[rjainv]

we can keep guessing what the original poster meant... .... ;P

 

[vikasbb]

[please specify ur question properly

 

[shiv_emf]

YEs ...
I think he meant to constrain combo logic ie .. module without any FlipFlips

 

[ray123]

you can not set constraint on a wire.
unless you create a submodule, and make that wire to be I/O of the submodule.