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Recent content by wandola

  1. W

    Relaxation Oscillator Jitter Simulation in cadence - Eye diagram confusion...

    Dear All, I am designing a conventional relaxation oscillator. The moninal frequency is around 2.85 MHz. When I try to run the transient noise simulation and use calculator to obtain the eye diagram, I got some weird diagram and i am very much confused. Attached you can see some waveforms...
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    ADC Measurement problem [Need expert opinion]

    Hi guys, I have designed a low-speed SAR ADC in a 65nm CMOS. sampling speed 1MS/s. The internal clock signal was about 5MHz. When I conduct the measurement, I found that the VDD (VDDAana, VDDdig, and VREF are all connected to the same PAD to 1.0V) changes for about 100 mV during ADC...
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    Need some suggestion in LDO frequency compensation

    I am designing the LDO for a SoC application. therefore, the otuput cap is about 5 nF. No external cap, no ESR ... I have no idea how the LHP zero comes into place... Right now the problem is that, the 3rd pole and 4th pole are at low frequency and they are also very close to the UGB and the...
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    Need some suggestion in LDO frequency compensation

    Hey guys, I have a three-stage LDO. The simulation result is in attached (without compensation). Looks like the dominant pole is only about 19 Hz, the second pole is around 90 kHz. UGB freq = 640 kHz. The dominant pole is too low. And the DC gain is too high. I tried to do a miller...
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    LVS check using Calibre

    for software issue, just email the vendor. Mentor will respond to u in one hour.
  6. W

    INL & DNL simulation using Spectre Cadence

    You got to do histogram testing. For simulation, i guess you may collect 20 samples per code. For 10-bit, u will need 1024x20 samples. The simulation time is going to take days.... of cos 20 samples is a very loose estimation.
  7. W

    Need some help with the small-signal circuit model

    Hey, Can anybody help me or explain to me how to develop the small-signal model of the circuit. The NMOS in one of the branches of the input stage is biased by some voltage. I think it will affect the 1st stage gain. Can anyone help me with this? The second stage is kinda of crazy. Usually...
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    ADC Testing Issue: Can anybody help me with this?

    Hey FvM, thanks for your help. I don't understand your meaning of operating the chip with output series resistors. Are you trying to say I can connect a resistor to the output? The output is digital output. In the measurement, I just connect the logic analyzer flying head to the output pin...
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    ADC Testing Issue: Can anybody help me with this?

    Hey crut, u can see some layout photos here. I didn't some testing. The results are not good. I can see a lot of missing codes. I did the testing several times. Some of the missing codes are not consistently appearing but some are. So I guess the ADC performance is actually affected by the...
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    ADC Testing Issue: Can anybody help me with this?

    I have designed a SAR-ADC. I am doing some testing now. I build the testing circuits. I have encountered some very funny issues which cannot be explained explicitly. I have attached a ppt slides I sent to my boss. The problem is that, when the output pad is loaded with something (just a...
  11. W

    Newbie designed PCB crosstalk problem: 5MHz clk cross coupled to GND

    I am a newbie. I designed a PCB without any supervision 'cause I have nobody to consult. It is a 4-layer PCB to test a ADC chip. The PCB is shown below. I found that my differential AC signals to the ADC input have been distorted. I think the clk signal is coupled to the the ground plane...
  12. W

    Customized digital circuit layout: any EDA tool for the layout?

    Dear All, I have designed a digital circuits for my ADC. The digital circuits is based on customized DFFs and some logic gates which are designed by me. I have also designed the layout for each digital cells used in my schematic. when I try to manually layout the whole digital circuits, the...
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    Bootstrapped switch Sample and Hold circuit - with dummy and without dummy

    Thanks a lot man. I understand now. That really helps.
  14. W

    Bootstrapped switch Sample and Hold circuit - with dummy and without dummy

    I also attached the two DFT plot here. It can be seen that the 2nd harmonic distortion for S/H with dummy is actually 1dB worse than without dummy. Is it possbile that the DFT plot is not correct? I did DFT with coherent sampling. Please take a look
  15. W

    Bootstrapped switch Sample and Hold circuit - with dummy and without dummy

    Dear all, I am designing a low-to-medium S/H circuit for an ADC. The sampling switch is a bootstrapped switch to linearize the on-resistance. I first designed a bootstrapped switch, and I simulated the waveforms and obtained DFT and THD in cadence with the calculator. After that, I also...
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