Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Recent content by vomit

  1. V

    Scope of variables and signals in VHDL and Verilog

    No, a signal declaration is only valid in a declarative context of a region containing parallel processes, such as a block or an entity. In the declarative part of a process you can only declare sequential stuff such as variables, procedures, functions to be used in that process. See...
  2. V

    using VHDL "if generate" with an input port

    No, the if..generate condition needs to be constant at elaboration time, not at runtime. So you can use constant expressions like x'length but not x itself. Because the value of x is only known at runtime.
  3. V

    Push button which can handle human weight

    Do a search for piezoelectric switches. They react on pressure and have no moving parts. Also: strain gauges.
  4. V

    Actual silicon, concept of "x" state

    You have two different concepts both modelled as "X". There's the X meaning "it could be zero or one, and I can't determine mathematically that it is one or the other". For example when using uninitialized memory, ... There's also a timing violation that may cause metastability. This metastable...
  5. V

    How to see the encrypted image in VHDL?

    vhdl binary file read Either you export it in Matlab in a text format (space separated numbers) and read it in via the VHDL std.textio library, or you write some sort of binary file with a known file structure (e.g. BMP) and parse it manually by reading it in as a "file of character" and...
  6. V

    Vhdl integer error????????????

    vhdl integer declaration Or perhaps try defining a type or subtype name in a package package MyComponentPack is subtype MyInt_t is natural range 0 to 32; end package; and use it wherever you need that kind of signal use work.MyComponentPack.all; ... port ( ... y : in MyInt_t; ...
  7. V

    WHAT IS THE RESTART PC CMMAND IN " C"

    If you want to schedule a reboot in Windows, try looking for the Setup API. https://msdn.microsoft.com/en-us/library/cc185682(VS.85).aspx There's a SetupPromptReboot function in there. https://msdn.microsoft.com/en-us/library/aa377413(VS.85).aspx
  8. V

    What's the equivalent of (ifdef) in VHDL?

    vhdl log2 #ifdef and macro expansion is a simple text-replacement, made by a preprocessor before the compiler sees the code. Therefore, #ifdef is not limited to processing and generating legal syntax. This makes it extremely versatile, at the cost of having no language knowledge at all. You...
  9. V

    Why Capacitor with dc motors??

    The continous switching of coils inside the motor would produce all kinds of brief high-frequency pulse currents. The capacitor close to the motor will discharge and deliver some energy to satisfy these current pulses, so that they don't need to draw current through the long (inductive) cables...
  10. V

    LATEX help- request for tutorial

    Re: LATEX help Try a visual LaTeX editor like LyX, that will be useful if you are a beginner. For examples: https://www.google.com/search?num=100&rls=en&hs=jmK&q=thesis+filetype%3Alatex
  11. V

    Electrolytic capacitor life-time

    electrolytic capacitor life Check at what temperature the 2000hrs is specified. A typical improvement of a factor of 2 for every 10 degrees °C lower can be gained. So if you go 30°C below the specified temperature, you gain a factor of 2^3 = 8. Check how the end of life is specified. If it is...
  12. V

    Inrush current limiting module for SMPS

    smps inrush current If you use a high side p-channel mosfet, you can use a zener/cap/resistor to ground to have soft start without extra voltages > Vinput. The R/C to perform the actual soft start, the zener to limit the gate-source voltage to whatever the FET requires. The only disadvantage...
  13. V

    why 200 ohm is used in ESD protection circuits?

    Re: why 200 ohm? There is no rule to use 200 ohm. Your circuit has it, but it may be any other value. It's a tradeoff between the advantages of - a high resistance (force a very low current in case a ESD voltage spike enters) - a low resistance (not too much voltage drop during its normal use)...
  14. V

    Basic VHDL Question about Edges

    increment vhdl As the DIV_SEL is a numeric value, you should change it from std_logic_vector to unsigned. After that, the process can be hugely simplified. CLK_OUT <= count(to_integer(DIV_SEL)); By the way, please remove the obsolete std_logic_unsigned library. The numeric_std contains the...
  15. V

    How to convert real value to logic vector in VHDL?

    real vhdl 0,00012207 is 1/8192, the finest precision you can represent in 13 bit. As you first multiply by 8192, then round to the nearest integer, and then divide again, you get a roundoff error of 1 least significan bit, or 1/8192. In other words: the result is as precise as it can get. Your...
See more

Part and Inventory Search

Back
Top