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Recent content by VLSI_CHE

  1. V

    Xilinx Cool-Runner II CPLD starter board

    Hi all, If we purchase Xilinx Cool-runner II CPLD starter board -> What accessories like softwares and liscence to implement the RTL on the target cpld are included with the purchase of starter board? Thanks in advance..
  2. V

    bufg followed by obuf

    a bufg followed by a obuf will give error in map in spartan6 as u said... but can that be used in a spartan3 device?
  3. V

    bufg followed by obuf

    why shouldn't we give out a clock (o/p of bufg) to an I/O pin? i am getting error during map phase.. is there anything wrong doing so? plz tell whats the right way to give out the clock.
  4. V

    case statement vs if statement

    What would be infered in the fpga for case statement and if statement?
  5. V

    what is a marginal design mean in fpga? how to overcome this?

    what is a DCfifo?
  6. V

    why do we need to avoid combinational logic in the code for fpga?

    yes, this is what meant. what happens in the routing if we do not bound the combnational logic with flops?
  7. V

    why do we need to avoid combinational logic in the code for fpga?

    can anyone explain ingeneral and in terms of internal fpga placement and routing?
  8. V

    what is a marginal design mean in fpga? how to overcome this?

    ca u plz suggest some guidelines for planning my clocks inside fpga..
  9. V

    what is a marginal design mean in fpga? how to overcome this?

    what kind of design mistakes need to be taken care of , in order to avod such margnal designs...
  10. V

    what is a marginal design mean in fpga? how to overcome this?

    can anyone explain what is a marginal design in fpga? why does that happen? what to do to overcome this problem?
  11. V

    Lattice - area vs speed optimisation option

    i am new to LATTICE FPGA. i want to the FPGA routing to be optimised to occupy minimum area(say) OR to be optimised such that speed is given highest priority during the routing in FPGA. is there any such option in lattice? if so plz help me out ....
  12. V

    What for are the 1.2, 2.5 and 3.3V used in Xilinx FPGA?

    ohk now i understood that each of the voltages given to the FPGA are for specified banks in it. i am using sparton 3 for now . so could anyone tell me the voltages used for it , the 1.2,2.5, and 3.3 used for the same reoson?
  13. V

    Can we generate a clock(say 1MHz) in FPGA without any input clock

    so can i conclude that we cannot generate a clock without any external clock input to the FPGA?
  14. V

    What for are the 1.2, 2.5 and 3.3V used in Xilinx FPGA?

    i want to know what for are the 1.2,2.5 and 3.3V useful in an FPGA.
  15. V

    Can we generate a clock(say 1MHz) in FPGA without any input clock

    i want to know whether we can generate a clock of any specified frequency using VHDL in FPGA without any external clock input to the FPGA. if it is possible to do so, plz tell me the way we can geerate it.
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