what is a marginal design mean in fpga? how to overcome this?

[VLSI_CHE]

can anyone explain what is a marginal design in fpga? why does that happen? what to do to overcome this problem?

 

[K-J]

can anyone explain what is a marginal design in fpga?

A design that just barely works. Or one that 'usually' works, but fails under certain conditions

why does that happen?

Usually the cause is inexperience of the designer

what to do to overcome this problem?

- Have the design reviewed by an experienced designer
- Learn from experienced designers

Kevin Jennings

 

[VLSI_CHE]

what kind of design mistakes need to be taken care of , in order to avod such margnal designs...

 

[TrickyDicky]

Avoid latches
Make sure all logic is synchronous
use proper techniques for crossing clock domain boundaries.

These are the biggest two problems.

 

[VLSI_CHE]

ca u plz suggest some guidelines for planning my clocks inside fpga..

 

[TrickyDicky]

Basically, try and minimise the number of clocks. Keep clock domain crossings to a minimum. And when you do, use a DCfifo.

 

[VLSI_CHE]

what is a DCfifo?

 

[TrickyDicky]

dual clock FIFO. It uses a memory as a buffer between the clock domains.