bufg followed by obuf

[VLSI_CHE]

why shouldn't we give out a clock (o/p of bufg) to an I/O pin? i am getting error during map phase..

is there anything wrong doing so? plz tell whats the right way to give out the clock.

 

[FvM]

The problem is about understanding the FPGA architecture and routing options of globals resources. I'm not a Xilinx expert, but I see in the Spartan 6 clocking user guide, that a ODDR2 primitive can be used to connect the global clock network (BUFG) to an output pin (OBUF). In addition, there are probably dedicated clock output pins assigned to specific DCM/PLL units.

 

[fpgadsgnr]

Clock outputs from PLL devices are sometimes routed through dedicated routing on the silicon, and synthesis tool is not supposed to insert IO buffers or assign them to the IO pins, PnR tool takes care of it.

 

[VLSI_CHE]

a bufg followed by a obuf will give error in map in spartan6 as u said... but can that be used in a spartan3 device?