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Recent content by vjabagch

  1. V

    Fixed Point Values Decreasing

    Thank you for the help. I have been comparing to the original distance (2D) but I think I might be capturing the wrong bits on my correction factor. I keep 3 separated look up tables. The look up tables are XY, XZ And YZ distances in 2D. Now I might be faced with some timing or...
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    Fixed Point Values Decreasing

    Just out of curiosity, could my original method of correcting the mutation be incorrect? I was originally finding a 3D distance to center. When I rotate incrementally I only work with 2 axes at a time. Therefore the third axis coordinate remains unchanged. So my new method is to find the 2D...
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    Fixed Point Values Decreasing

    I was thinking that perhaps my limited precision is causing the error. I use 14bits (sign bit included) for x, y, z. Monitor resolution is at 512 X 512. The correction factor which I multiply by the rotated coordinate is very close to 1 which is making me think that I don't really offset the...
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    Fixed Point Values Decreasing

    I have a design that renders fixed point coordinates of a 3D object on a monitor. The design is implemented on an FPGA and outputs the signal to the monitor. I am applying 3D rotation transformations across X, Y, and Z axes. When applying the transformation the object keeps mutating and...
  5. V

    : DVI interface in virtex5 lxt110 problem

    I too was stuck on this point when I realized finally that I had to multiplex the 12-bit data streams. You need to first formulate your data of 24 bits RGB (8 bits,8 bits,8 bits). Then take the upper 12 bits and send it to the first part of the multiplexer and the lower 12 bits to the second...
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    FPGA 3D GPU - Loading of 3D Coordinates on RAM

    Are you storing your image in block ram or perhaps some memory on the FPGA? Just count through the addresses (your input will be a start address and end address) then initiate a count update at every clock cycle. Line drawing requires a start and end coordiante (xy) start and (xy) to find...
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    Hardware verification languages

    Parev Mkrtich, I have taken one class on SystemVerilog for verification. I know Verilog but am also a novice in verification as well. Try SystemVerilog because it has many constructs supported for both verification synthesis and it is object oriented. I can supply references if needed...
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    FPGA 3D GPU - Loading of 3D Coordinates on RAM

    Hello pratik_r, Thank you for your question. It is great to hear your interest in this topic. I too find graphics an exciting field. If I understand correctly are you trying to do a line generator in combination with a object coloring module (filling)? I do not know bit blitting but if you...
  9. V

    How do I generate the conditions of a case statement in Verilog using a loop?

    After some thought I concluded that it was better to include a loop instead of a full case statement. The loop (non-synthesizable) will run until the desired angleIndex and calculate the angle based on the angleIndex * deltaAngle which is 6.28 radians / 1024 steps / cycle. real angle; real...
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    How do I generate the conditions of a case statement in Verilog using a loop?

    I have tried generating the conditions for my case statement using a generate, endgenerate block and I am unable to get it syntactically correct. Is my intended usage of generate supported by Verilog and what, if any, changes are needed to make it compile correctly. Ignore the lack of brackets...
  11. V

    Load program into the Flash on S3E and set up to load into FPGA on power up

    I would suspect to say that you need to check the dip switch (the one on the board that instructs the FPGA which location to load the design from) to make sure they correspond to the right mode and then try to alter the clock source setting and frequency on the prom fpga interface on Impact...
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    Load program into the Flash on S3E and set up to load into FPGA on power up

    The design should load upon power up. There is no need to press the PROG button. Have you tried initializing chain in Xilinx Imapct boundary scan when your device is powered on. Do you have settings set to similar settings as to what the image below not exactly the same but similar? Also...
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    Load program into the Flash on S3E and set up to load into FPGA on power up

    Have you gone through the prom formatting step? Once you create the mcs file in Impact then you initialize the boundary scan chain at which point you would would run the program command. I had some difficulty at first like you but its really quite easy. Just wait some time for the design (if...
  14. V

    Image via HDMI using SPARTAN 6.

    Just curious if you have included the UCF file with your project? Usually when I do not get any response from the FPGA it is because I have not included valid UCF file with the source code. Also, where do you want the image to appear? Center, repeated, stretched...etc? If you want to center...
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    Frame buffer and clock speed question for Virtex 5 board

    I have been trying to get a diagonal line to show up on my screen using a Virtex 5 (V5LX110T) board. It has an external ZBT SRAM chip which I am using as a Frame Buffer. So far, I have written a series of sequentially incrementing data values at sequential memory locations and have been able...
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