zuhaib
Newbie level 1
Hello,
I have a .jpeg image. I converted it into a raw r,g,b image. After that I converted it into a hex file. I am using that file as an input and want to view the image via HDMI output port onto the monitor. I am using the demo XAPP495 .PDF document and modified the module hdlcolorbar.v, The modified code is:
module hdcolorbar(
input i_clk_74M, //74.25 MHZ pixel clock
input i_rst,
input [10:0] i_vcnt, //vertical counter from video timing generator
input [10:0] i_hcnt, //horizontal counter from video timing generator
output wire[7:0] o_r,
output wire[7:0] o_g,
output wire[7:0] o_b,
input wr_e
);
wire addr2;
videoram video_inst (
.r (o_r),
.b (o_b),
.g (o_g),
.clk (i_clk_74M),
.rst (i_rst),
.addr (addr2),
.we (wr_e)
);
assign addr2 = i_vcnt[3:0]*16+i_hcnt[3:0];
endmodule
The video ram block is:
module videoram(clk, we, addr, din, r, b, g, rst);
input clk;
input rst;
input we;
input [7:0] addr;
input [23:0] din;
output reg[7:0] r;
output reg[7:0] g;
output reg[7:0] b;
reg [23:0] ram [0:255];
initial
begin
$readmemh("test.rbg",ram);
end
always @(posedge clk)
begin
if (rst)
begin
r <= 0;
g <= 0;
b <= 0;
end
else if (we)
ram[addr] <= din;
begin
r<=ram[addr][23:16];
g<=ram[addr][15:8];
b<=ram[addr][7:0];
end
end
endmodule
And in the vtc_demo.v, I have only modified the hdlcolorbar module as:
hdcolorbar clrbar(
.i_clk_74M(pclk),
.i_rst(reset),
.i_hcnt(bgnd_hcount),
.i_vcnt(bgnd_vcount),
.o_r(red_data),
.o_g(green_data),
.o_b(blue_data)
);
I have successfully synthesized the code that is there is no error in the code but it doesn't show any image. The image is 16x16. Can anyone have the idea where the problem is?
Regards
I have a .jpeg image. I converted it into a raw r,g,b image. After that I converted it into a hex file. I am using that file as an input and want to view the image via HDMI output port onto the monitor. I am using the demo XAPP495 .PDF document and modified the module hdlcolorbar.v, The modified code is:
module hdcolorbar(
input i_clk_74M, //74.25 MHZ pixel clock
input i_rst,
input [10:0] i_vcnt, //vertical counter from video timing generator
input [10:0] i_hcnt, //horizontal counter from video timing generator
output wire[7:0] o_r,
output wire[7:0] o_g,
output wire[7:0] o_b,
input wr_e
);
wire addr2;
videoram video_inst (
.r (o_r),
.b (o_b),
.g (o_g),
.clk (i_clk_74M),
.rst (i_rst),
.addr (addr2),
.we (wr_e)
);
assign addr2 = i_vcnt[3:0]*16+i_hcnt[3:0];
endmodule
The video ram block is:
module videoram(clk, we, addr, din, r, b, g, rst);
input clk;
input rst;
input we;
input [7:0] addr;
input [23:0] din;
output reg[7:0] r;
output reg[7:0] g;
output reg[7:0] b;
reg [23:0] ram [0:255];
initial
begin
$readmemh("test.rbg",ram);
end
always @(posedge clk)
begin
if (rst)
begin
r <= 0;
g <= 0;
b <= 0;
end
else if (we)
ram[addr] <= din;
begin
r<=ram[addr][23:16];
g<=ram[addr][15:8];
b<=ram[addr][7:0];
end
end
endmodule
And in the vtc_demo.v, I have only modified the hdlcolorbar module as:
hdcolorbar clrbar(
.i_clk_74M(pclk),
.i_rst(reset),
.i_hcnt(bgnd_hcount),
.i_vcnt(bgnd_vcount),
.o_r(red_data),
.o_g(green_data),
.o_b(blue_data)
);
I have successfully synthesized the code that is there is no error in the code but it doesn't show any image. The image is 16x16. Can anyone have the idea where the problem is?
Regards