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Recent content by vinayshivakumar

  1. V

    Dynamic Logic in the ASIC industry

    Re: Dynamic Logic Not the DRAM , I wanted to know about dynamic combinational logic - domino logic etc. whether they are used anywhere ?
  2. V

    Dynamic Logic in the ASIC industry

    Dynamic Logic Hi All, I have been into ASIC physical design for quite sometime (~3yrs), but have never used dynamic logic. Can anyone tell me how widespread is the use of dynamic logic in the ASIC industry ? Are they used at all ? Regards, Vinay Shivakumar
  3. V

    MAGMA : BUFFER COUNT MINIMIZATION

    Try bumping up the tau for your library before doing run gate buffer wire. This will reduce the buffer count by forcing the tool to size rather than insert buffers to meet timing. you will have fewer cells but larger ones. This in certain designs helps....
  4. V

    Difference b/w Test chip and normal chip

    Test chips are chips which contain IP blocks which are not silicon proven.. Testchips might also be for validating a library or technology...
  5. V

    who can tell me "what is Transition " ?

    Transition should be set based on the library being used
  6. V

    Different processes with the same process size

    do you have anydocuments on MTCMOS
  7. V

    Pls. explain clock phase & skew phase

    clock phase - when you define a clock two clock phases are created (one for rising edge and one for falling edge) - clk:R and clk:F. "A clock phase is the basic element of a clock. Each clock domain created with the force timing clock command creates two clock phases: one for the rising edge...
  8. V

    For auto layout, SE or Encounter?

    SE is very very old.... It has no physical synthesis options (i had serious issues fixing even load and slew violations with it) , and i guess its capacity is very limited.. There is no interclock skew balancing... Moreover it is not a DSM product... I dont think it can work well at and below...
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    Different processes with the same process size

    Hi , I have a few queries : What is the difference between vt classes in a library ? What factor do they change to change the threshold voltage (vt) ? What is MTCMOS ? Any Docs on that ??? What is the difference between a mixed mode process and a normal cmos process - for example IBM has 3...
  10. V

    What are tap cells and what is the usage of them?

    Re: tap cell? @kumar_eee thanks @vlsitechnology Thanks. Which document did you pick this info from... I had searched a lot for data on it , but never found any stuff....
  11. V

    Hold slack!! Query, how to find hold slack time

    Re: Hold slack!! Query If you want to understand timing calculations, there is nothing better than primetime documentation - pt user guide fundamentals . Download it from here (little dated though): asic.ee.cuhk.edu.hk/ptmsc/ele7260/ptugf.pdf
  12. V

    Open Access & DFII - How these differs from each other?

    Re: Open Access & DFII Open access is the new open database format promoted by cadence. DFII is th older proprietary format.
  13. V

    Query regarding process geometry

    Hi, what is the rationale behind choosing on the process geometry ? For example why 45 nm and not 46,47,48 nm ?????
  14. V

    MAGMA ANTENNA VIOLATION

    antenna violation fix I think you ca n try jogging to a layer below...
  15. V

    Gated Clock Advantage and Disadvantage

    what are the disadvantages of a digital clock Gated clock - Difficult to verify in GLS , Physical perspective - more insertion delay for clock tree Inreases area , complicates timing closure with all the clock gating checks.... (just a lil bit)
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