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Recent content by vikram789

  1. V

    Requirement of posedge flop after EDT

    Hi , Why do we require that only a posedge flop be encountered in a scan-chain . Also is there any document from where i can get understanding of functioning of EDT P.S, I belong to Synthesis domain
  2. V

    What does it mean that the hold relationship is from first edge to first edge?

    Hi, i read somewhere that "hold relationship is typically from first edge to first edge" what is mean by this statement
  3. V

    How are stare retention flip flop/registers implemented in hardware?

    hi can someone explain me how stare retention flip flop/registers are implemented in hardware
  4. V

    substrate biasing and Multi-Vt cells

    Hi Eshwar, I agree with you but my concern was that final result obtained is same in both cases. Thanks Vikram
  5. V

    substrate biasing and Multi-Vt cells

    What is the different between following low power implementation techniques:- 1.using multi-Vt cells. e,g. Low Vt , High Vt 2. using substrate biasing
  6. V

    Tie Cell with explaination

    Hi guys, can someone explain me working of Tie cell with a diagram
  7. V

    Power management Unit - CLP

    i am fresh graduate just starting with CLP, so some basic info about tool , what it intends to do....
  8. V

    Why leakage in lower technology nodes is increasing?

    why leakage in lower technology nodes is increasing
  9. V

    what is loading effect

    thanks for explanation.......can you explain loading effect considering Digital Domain and Mos. The scenario is that a Low Voltage detector(LVD) is detecting when the o/p voltage of a particular unit goes low so that it can trigger Voltage Regulator. i came to know that o/p voltage that is...
  10. V

    what is loading effect

    can anyone explain me loading effect in detail and thereafter explain the statement that "loading effect cumulatively decreases the voltage supply"
  11. V

    Power management Unit - CLP

    Hi i am working on CLP , can anyone give me some info on Power Management Unit
  12. V

    High-to-low level shifter

    @colibaidh The circuit you have given, gives inverted output LOGIC 1 = 3.3V gives LOGIC 0 (1.8V) and LOGIC 0 = 3.3V gives LOGIC 1 (1.8V) and Interchange the connections of two 3.3V NMOS to get rid of the problem Thanks Vikram
  13. V

    wire acts as a which type of filter

    wire acts as a which type of filter :high pass or low pass ?
  14. V

    info on level shifter

    hi i need info on level shifter which are used in IC for saving power. i need ckt and working
  15. V

    why power switch use a PMOS only

    why NMOS cannot be used in Power Switch
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