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Recent content by viju

  1. V

    set_max_delay for CDC path

    Hi lostinxlation, Thanks for your reply. Can you please explain me in detail regarding your statement " but, in general, using max_delay is the correct way to implement the clock domain crossing". I can understand that if we have a handshake mechanism (lets say data bus is synchronized using...
  2. V

    set_max_delay for CDC path

    Hi My design has got 3 clks. In our design there is no logic in the CDC path i.e. in source domain output of block is flopped and sent to destination domain and it is also flopped (by 2 flop synchronizer). So there is not logic between 2 flops. I know that its standard practice to declare a...
  3. V

    Do we need to set uncertainty on generated clocks also ?

    yes. As tool don't have idea that generated clk is up scaled or down scaled. So tool can not take same(master clk) uncertainty value on the generated clks.
  4. V

    Spy glass CDC analysis with FIFO based design

    Hi Sakshi, Thanks for help. I tried to put enable_fifo and enable_handshake in sgdc file but it didn't worked. It says unknown command for both options. it used with out - i.e. just new line of sgdc file enable_fifo similarly new line for enable_handshake Can you please show me example of...
  5. V

    Spy glass CDC analysis with FIFO based design

    Hi , I have a design which has many FIFOs in it. I'm running SPY Glass CDC analysis on it. What I found it report is that Spy Glass is not able to detect the FIFO architecture and generates lots of Error / Warnings like "Data hold check:FAILED" Ac_cdc01a. for the wr and rd pointer flops. It...
  6. V

    Area reduction after synthesis with scan

    Hi, I have noticed that when I do synthesis with scan, the area is reduced. Can any one make me understand how it is possible? In face by scan logic we are adding some logic in front of flops, so how come area is reduced. Please share your views/experience for it. Thanks, VJ
  7. V

    different libraries G GP

    Hi , Can any one help me in understanding the difference between library with G only and Gplus? e.g. TSMC 65 nm G TSMC 65 nm Gplus TSMC 65 nm LPe what is difference in all above? I know LP stands for Low Power, but what is "LPe"? What is meaning of tapless library? does it mean that all the...
  8. V

    Need Paper : Arbitration Approach of Efficient Bandwidth All

    Hi I need the paper on arbiter mentioned below. I'm able to find the paper but cann't download as it is on chines web-page. Title : An Arbitration Approach of Efficient Bandwidth Allocation and Low Latency for SoC Communication Authors : LU Junlin, LIU Dan, TONG Dong, CHENG Xu MicroProcessor...
  9. V

    What does LPe in 40 nm LPe library mean?

    Hi , Can any one please tell me that what is meaning of 40 nm LPe ? I can understadn LP stands for Low power , but what LPe signifies? I observed with other node libraries as well... Is there any standard database from which we can interpret the meaning of this encoding? Thanks, Tarang
  10. V

    Question on report_timing command in DC

    Hi , I have doubt in report_timing command of DC. In command : report_timing -delay max -nworst 1000 > setup_report.rpt what is meaning and significance of option -nworst 1000 ? I Does it specifies number of violating paths or some thing related to hierarchy? Please guide. Thanks.
  11. V

    dc Vs primetime: reasonable slack or not?

    What is finally concluded? This is a really a interesting topic for me. Please comment. CIE40 ; Will setting set auto_wire_load_selection "false" will solve this problem/ Thanks
  12. V

    Verilog Generate statement to declare a `define

    Hi, here is my pseudo code... " `timescale 1ns/1ns module test(); reg a; reg b; parameter text1 = 1'b0; generate if(text1 === 1'b1) begin `define ONE1 initial $display("\n\n%m : LOOP ONE....\n\n "); end endgenerate generate if(text1 === 1'b0) begin `define ZERO1...
  13. V

    Using AHB split transfer in FSM

    retry split Hi , The split transfer should be given when you as a slave sure that you will take huge time (in terms of clock cycles) to give response to Master from which you got the request. spec says..."The SPLIT and RETRY response combinations allow slaves to delay the completion of a...
  14. V

    Ask for help!How to encrypt the netlist?

    protect-endprotect ncsim in VCS, the code between `protect and `endprotect will be protected and will be stored under filename.vp once you simulate it.
  15. V

    Slow Simulation - simulation slow state count

    Slow Simulation Hi Ajeetha, From your reply, I have a one question for you. Based on your vast experience can you please tell me how much memory(execution speed) the assertions (SVA) will take? I mean how much overhead will be on simulation time due to SVA? I would also like to know from...
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