Slow Simulation - simulation slow state count

[Digital-L0gik]

simulation slow state count

Hi,

I am running a rtl simulation of a state machine in NCSIM and its taking a long time to complete. The state machine implements large counters for long delay times. However, simulation is going extremely slow. I have outputted the count of of sims using display statements for debugging purpose. In the beginning, the count increments fairly quickly, however, with time it slows down. Does anyone know why this is and how I can possibly speed things up?

 

[RBB]

ncsim assert warning

Turn on profiling (+profile), which will write out a text file showing what line(s) the simulator is spending most of its time.

 

[Digital-L0gik]

Re: Slow Simulation

I know where its being slow because my debug output using display statements is showing the status of my count with each cycle. It progressively gets slower. So why would something like the following be causing such a huge slow down?

always_ff @(posedge clk)
begin
if (rst == 1'b1) count <= '0;
else
if (done ==1'b0 && state==count)
begin
      count <= count + 1'b1;
      $display("Count: %b:", count);
end
end

always_comb
    done = (count == 16'b 1111_1111_1111_1111 ? 1'b1, 1'b0);

My test bench has a clock of 120 MHz clock.

Added after 20 minutes:

Thanks for the profile tip dude it worked hahahaha. It was pointing to sv assertion I wrote that apparently hogs memory over time!

 

[ljxpjpjljx]

Re: Slow Simulation

in fact, the simulation speed is related to the PLI and display command!

 

[aji_vlsi]

Re: Slow Simulation

Hi,

Thanks for the profile tip dude it worked hahahaha. It was pointing to sv assertion I wrote that apparently hogs memory over time!

That is quite a possibility if you have multiple threads in the antecedent of a property. If you show your SVA code we can help better.

BTW, we cover that exact topic of multiple threads in our SVA class.

Regards
Ajeetha, CVC
Next SV course starting in Feb 09 end. See:
https://sv-verif.blogspot.com for details

 

[viju]

Slow Simulation

Hi Ajeetha,

From your reply, I have a one question for you. Based on your vast experience can you please tell me how much memory(execution speed) the assertions (SVA) will take? I mean how much overhead will be on simulation time due to SVA?

I would also like to know from performance perspective that if I implement the protocol checking mechanism with verilog code v/s SVA. Which one is better in terms of simulation speed?

Pl. try to answer all the questions...

Thanks in advance...

 

[Digital-L0gik]

Re: Slow Simulation

assert property ( @(posedge refclk) 1'b1 ##[0:$] (state == RUN)) $display("Pass");
|
ncsim: *W,RUNAWY (./sequencer.sv,193|5): Unusually large number of attempts in progress.
assert property ( @(posedge refclk) 1'b1 ##[0:$] (state == RUN)) $display("Pass");
|
ncsim: *W,MEMHOG (./sequencer.sv,193|5): Requires increasing memory over time.

This is the assertion and the warning the profile command gave me in NCSIM. I wanted to write the assertion to test if the simulation would hit a critical state at some point between the start and finish of the simulation. However, the way I wrote the assertion ( I am new to assertions) spawns a new assertion instance every clock tick thereby slowing down simulation drastically. The dut which is basically a state machine that changes states after long delay times was not completing simulation even after 8 days of run time. After commenting out the assertion and adding a simple display statement, the sim completed in less than a minute haaha!