Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
whold you please explain more .do you mean of dual power two supplies (vdd & vss )? if so, you have to design your circuit in such a way that the output common mode level becomes zero not to remove it.
somewhat .It depends on your wire resistance and length and the material from which the wire was made and also the environment . but generally in any kind of signal transmitting such as audio and etc if you use twisted pair wire any noise and other unwanted signals that maybe it picks up will be...
because if you don't have enough bw or sr your high rate or high freq signal will be distorted or deformed because your system won't be able to track your signal fast variations ( for analog cases ). in digital ones having more bandwidth provide the capability of more data transferring and...
it depends on relation between your parameters(A,B,..) would you please give more details. your tf has three poles and which one has the minimum value will be your domonant pole.
but the transistor in common base configuration isn't an inverter!
- - - Updated - - -
I don't have your schematic completely . but if your mean of series transistor is transisitor in common base configuration they don't play as an inverter. sometimes we use them in amplifiers as a cascode...
maybe you have some convergence problems sometimes are explained in the log .don't you.
check your circuits connections carefully and your pss analysis parameters and the tones you've given before.
I have an sram memory . it's data width , address bus width and depth all are parametric.my sram depth is d and the address bus width must be log2(d) and represented by c parameter . I import the math function library by several methodes in my code but neither of them worked and there were...
I am going to design an LNA for 60ghz or higher . I have read some texts and papers but I couldn't gain a good viewpoint about of which type of inductor ( transmission lines , active inductor , pasive spiral inductor ) I have to use in my design with respect to all things such as area , power ...
Can anybody introduce a good book for communication circuits?
I red the clarke and hess one before but I think it is so classic and primal (isn't it?)
do you know which books for communication circuits are being taught in mit or stanford or ucb universities?
thanks.
I want to add some pad to my tsmc18rf tech file. I have tried both methods : by copying the dvio library that contains the sig_pad library, into the tsmc18rf. and by adding those libraries from the tools\library path editor\... . but there was no changes in my lsw window. and there was no pad in...
I have layouted an LNA and mixer . there is an error in LVS says the ntap is connected to gnd! and the error marker refers to the nwell of caps. I connect the bulk or pwell of transistors and caps to gnd . for the sake of this error i connect the nwell of caps and transistors to the vdd. for the...
I have designed a front-end and now i want to layout it in cadence and post layout it using assura. but there is some problems in extracting .in extracted file at both of the LNA and mixer , all of transistors have the width fixed to 15u , capacitors to 30fF, all kind of resistors to 5.62k and...
i think getting the negative capacitance is because of the direction of the current and the variation of q.that causes the negative sign in derivetive equation.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
