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Recent content by vhdl34

  1. V

    trying to generate a random number in a particular range using lfsr

    i m using lfsr to generate a number from 145 to 786 howwver the same 3 numbers are appering can you please help me here under is my code library IEEE; use IEEE.STD_LOGIC_1164.ALL; USE ieee.numeric_std.all; entity random is port ( clkin : in std_logic; random_num : out integer...
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    display port vga vhdl coding

    im trying to display a whole screen red however its not being possible im using 640 by 480 screen and im timing on25 mhz clock and refresh at 60 hz here unde ris my code can some one help me find the mistake library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use...
  3. V

    an error in translate when using xilinx

    can you please explain what i need to do as i m stuck here :( i really appriciate if you help me thanks
  4. V

    an error in translate when using xilinx

    this error is occured when im trying to translate this code the error is the following Started : "Translate". Running ngdbuild... Command Line: ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc testingmon.ucf -p xc6slx16-csg324-3 testingmon.ngc testingmon.ngd Process "Translate" failed and...
  5. V

    coding vga port vhdl

    yes i need however to code the timings
  6. V

    coding vga port vhdl

    im going to use 25 mhz
  7. V

    coding vga port vhdl

    yes to have all red pixel
  8. V

    coding vga port vhdl

    im trying to display a red box on a 640 by 480 screen however nothing is displayed on my vga screen im using nexys 3 and these were the port used clk v10 ns-n6 vs -p7 red1 -u7 green2 - p8 blue2 -r7 here under is my code which i made thanks i appriate any help library IEEE; use...
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    vhdl multiplier 4 bit by 4 bit design with shift registers

    hi, i realized what the problem was. however i cant really rearrange it in order to make this work i need to shift the multiplier to the right and the multiplicand to the left on every clock cycle however i cannot make it can you help me to do that pls. i updated my architecture and tb these...
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    vhdl multiplier 4 bit by 4 bit design with shift registers

    thanks but i having a problem with the counter im assigning the counter to "0000" and add "0001" however the counter is ahving a value of "1000" in the beginning of the program what can be the mistake and i have another question is the syntax correct variable reg : std_logic_vector(3 downto 0)...
  11. V

    vhdl multiplier 4 bit by 4 bit design with shift registers

    hi im trying to make a mmultilier of 4 bit by 4 bit here under is my code however i have some problems as its not working. it diviide the program in two clock cycles by the state however the program is not changing any type of help is reallyy appreciated thanks library IEEE; use...
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