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It sounds like what you're trying to do is simple file i/o and that is supported directly by the verilog and vhdl languages. You just need to setup a testbench that reads the input file and applies it to a top-level pin of your design. To capture the data you're interested in your testbench...
address counter vhdl
Hi vinodkumar ,
i the above code , the first is
if(clock='1' and clock'event)then
ur trying to impement sync counter , so don't put reset and counter in the sencitivity list
Regards
venkatesan
ddr2 sdram module virtex4
Hi yasamin ,
i am also got the same but in virtex-5,
the problem is in the memory code (micron memory core ) and there is no problem in RTL genearted by MIG so don't worry
try the same procedure with cypress memory you will get the signal...
Re: Microcontroller FPGA
Hai siongboon,
go to the link given belowlearn about the basics of fpga
https://www.altera.com/servlets/searchcourse?num=103&start=0&total=103&forwardto=coursecatalog&showall=1
lvcmos lvttl
see this
Voltage Levels Description:
Comparison of Input and Output [I/O] logic switching levels for the CMOS, TTL, mixed CMOS/TTL, ETL, BTL, GTL, and Low voltage glue logic families. The graph above provides a comparison between the Input and Output [I/O] logic switching...
hi ,
in Behaviour level, process keyword is present
in dataflow level , concurrent statement (<=) is present
and if both are present it is mixed level model
Re: vhdl code
process
begin
clk <= '1' ;
wait for 500000 ns ;
clk <= '0' ;
wait for 500000 ns ;
end process ;
this code will generate thew clock of 1kHz
any dbout
give your mail id
dear all ,
now currently work with ACTEL FPGA
for i am using ACTEL IDE tool
in this design i have one problem
while i simulate and synthesis
ERROR: Mismatch between the portlist of the...
dear all ,
i done project on PICO-processor using SPARTAN-3E
it sythesis but while doing post-sythesis simulation it show error like below
FATAL ERROR : NetlListWriters:Nlw_NetlistWriter.c:954:1.117.10.1
please any one help me very urgent
thanks all
Re: vhdl help
can u please tell me how to use a package in the vhdl ?
for this
do the library declaration and then creat package
by using this "use work.packagename.all ;
use in your design
and how to write function that return more than one output...
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