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Recent content by vaidhyanathan

  1. V

    reverse short channel effect

    I read in article that "At short channel lengths the halo doping of the source overlaps that of the drain, increasing the average channel doping concentration, and thus increasing the threshold voltage. This increased threshold voltage requires a larger gate voltage for channel inversion...
  2. V

    channel length modulation

    I read that in an n-mosfet, when drain voltage is increased above threshold (in saturation mode) the inversion channel between the source and drain is pinched-off near the drain region. so the channel length decreases and so its resistance. so larger current flows through the channel. My doubt...
  3. V

    electronic elementary questions

    The opeartion of BJT (ON or OFF) is dependent on the value of bias voltage(Vbe). But why it is called a current controlled device?
  4. V

    electronic elementary questions

    i got it now.Thanks a lot Mr.LVW for your explanation.
  5. V

    electronic elementary questions

    dear LVW, can i interpret your answer like this? In a forward biased pn diode, the depletion width is low and current(due to majority carriers) flows from p to n. when it is suddenly reverse biased, current(due to majority carriers) of same magnitude flows in the reverse direction for a short...
  6. V

    electronic elementary questions

    what happens exactly in a p-n diode during reverse recovery time? can anyone explain me in terms of minority and majority charge carriers? thanks in advance
  7. V

    basic digital electronics

    thanks a lot dude:grin:
  8. V

    basic digital electronics

    why active low devices are preferred to active high devices:?:
  9. V

    basic digital electronics

    Why the power dissipation is more during the transition of clock rather than during the levels 1 and 0:?: thanks in advance
  10. V

    analog circuits design

    Is the physical dimensions of a transistor used in the fabrication of gates, related with propagation delay of that gate? If so, please explain me how....
  11. V

    digital design using logic gates

    why pmos is used as pull-up and nmos as pull-down? why not the other way round? thanks in advance...
  12. V

    digital design using hardware description languages

    thank u very much for ur reply.. do you mean that all delays including inter statement delays are also non-synthesisable?

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