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I am familiar with some steps, but I only worked in EDA software companies, and not in companies actually developing ASICs.
My understanding is that the following steps are involved:
1. Specification is developed and approved
2. Verilog is written
3. Verilog is simulated (ex. Verilator)
4. The...
I am wondering if there are sensors that can measure distance to other objects up to 2-3 inches out?
For example, the sensor might use reflected light, or radio signal that is reflected by some other nearby part to determine distance between them.
"and21" isn't a valid cell name.
I think that the problem is that fusion compiler creates the GDSII file with only wires, and no transistors. The last instruction before "write_gds" is "route_auto".
I think that FC functions fine, it places all wires.
But transistors are added by some other...
> looks like the the gds is generated incorrectly, the cells are not present. only the wires
Yes, I agree.
How can I understand why cells are not present?
I only defined one cell. Other cells must be standard cells.
What steps can I take to understand why the produced GDS file is invalid?
Synopsys and Intel posted the challenge to solve Sudoku puzzles using the VC Formal software.
They say that at Intel they use Sudoku puzzles to train formal verification engineers.
I am a little familiar with VC Formal: it can analyze Verilog code and find issues like arithmetic overflows...
I've ran the Fusion Compiler on a simple module:
module top(a1, a2, z);
input [0:0] a1;
input [0:0] a2;
output [0:0] z;
assign z = a1 | a2;
endmodule
Fusion Compiler generated the GDS file that KLayout shows like this:
I have trouble relating the original...
I am curious: is GDS sent to the fab and the fab does further processing like OPC, or further steps are also a responsibility of the fabless semiconductor company?
I have the x.nlib library directory with many HDL libraries linked there.
I can run the commands:
1. open_lib x.nlib
2. read_verilog my.v
3. write_verilog -include all -hierarchy all x.v
Library cells used in my.v that are present in HDL libraries do not appear in x.v, despite the "-include...
@oratie
I tried to run FC-RM_U-2022.12 but it fails to run simple Verilog modules. It fails with errors like:
Do you know what is the minimal tcl script that can compile a simple Verilog module to GDSII?
I am using a simple single module verilog with Synopsys FC-RM_U-2022.12 scripts.
The init_design stage fails:
Earlier in the log the 'Basic floorplan and design checks' failed:
What are "site rows" and "site arrays"? Why do RM scripts expect them? What are "signal terminals", "tracks" and...
While installing the Synopsys Fusion Compiler this error message pops up:
Can't install U-2022.12-SP1 release of fusioncompiler: Missing required common package
Unfortunately it doesn't say what package is missing.
There are several reference methodology downloads on solvnet that have the word 'compiler' in them: Design Compiler, Fusion Compiler, IC Compiler, IC Compiler II.
Are all of them able to compile from RTL to GDS? What is the difference between them?
I am mostly a software person, but I can program in Verilog and I understand the ASIC design workflow in general.
Through my job I have access to all Synopsys tool licenses.
Is there a concise tutorial that describes step by step how to run Synopsys tools to build GDS from Verilog...
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