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spectre problems encountered during simulation
ya, the output file is 0 Kb. Only the netlist was produced, the simulation just getting started and immediately it is getting stopped with the above message. It is not storing anything into the file.
problems encountered during simulation
Hi,
I am running mixed signal simulation in spectre-verilog simulator with digital blocks implemented using verilog and analog blocks with transistors in spectre. I have created a 'config' view to simulate it.
When I try to click 'netlist and run'...
Hi,
Could anyone please help me running vhdl code integrated with circuits developed using spectre simulator. I need it to run in spectre itself. I ran with veriloga codes. It seems to be working along with designed circuits in spectre but then it is generating errors with vhdl.
What should be...
which latch is used mostly in digital
one is to store data and another is that latch will increase the speed of the comparator after the initial preamplification is done.......
I am sorry, I was thinking it is a folded adc or folded op amp when I said it will result in increase in power. I still argue that folding of standard transistor might result in a slight increase in the delay because of the extra parasitic caps and res associated with the routing between...
In a pipeline ADC, you may or may not want to scale down the capacitors. You could have the same capacitor size and still could implement the RSD logic. Anyway coming to capacitor values, from whatever I have read, I would stick to 100f for better matching. Somebody who had first hand experience...
It mostly depends on the application you are working on. If your circuit can withstand mismatch then you can layout a capacitor of much lower value. You also need to worry about the kT/C noise. Usually the mismatch would be normal distribution and could also be approximated as delta(C)/C...
Re: how to set equal time step of transient simulation in Ca
I can see another option called "step" apart from "maxstep" in the options for transient simulation.....did you check your simulation by inserting a value in step alone instead of inserting a value in maxstep
'input.scs' is a file which carries the netlist information, any variable values used in the design, all information that are stored in a 'state' of a typical Analog Design Environment and it also contains the outputs that are to be plotted.
It is the output file usually stored in the...
Could anyone help me in providing the scripting code for running the input.scs file in Cadence, thereby I wanted the netlist to be simulated and run, and also the outputs to be plotted?
Thanks,
Shankar Thirunakkarasu
that is what i used after trying out with one delay element......anyway thought of knowing what actually would be the problem with a single delay element.......
Thanks for your response.....
Hi,
When I use an ideal "Delay" block from analogLib in Cadence, with differential signal at its input, it gives the output only at its negative terminal and doesnt provide a differential output. The positive terminal is getting grounded. I would be happy if anybody could share of what is...
Hi,
Could anyone please clear me whether the conversion gain in mixer model of ADS refers to Voltage conversion gain or Power Conversion gain?
Thanks,
Shankar.T
capacitive kickback
so is there a solution to avoid this current spike. in inductor we use an diode to stop the voltage spike.....here could you think some other device.....since we cannot have a diode here....
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