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Recent content by tramu

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    SFP Power supply inductor

    Dear sir, I want to select an inductor for SFP transceiver power supply filter circuit. Please find the attached schematics for the reference. How to select an inductor ? Any inductor with 1micro Henry, & DC resistance <1 Ohm specification is enough ? I would like to know what are the other...
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    Routing guidelines of UTOPIA-L3/POS-L3 bus

    Hi, I want to connect UTOPIA-L3 TX & RX signals between master & slave. Can anyone have any experience in routing UTOPIA-L3 data signals. Please recommend/share any document which mentions the routing guidelines for UTOPIA-L3 32 bit bus(for both Transmit & Receive). Regards, Thulasi
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    Why Memory devices doesn't have JTAG interface

    Dear, I don't see any memory with JTAG interface. Why memories generally do not have JTAG though they are coming in BGA packages? Please respond. Regards, Thulasi
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    Parallel NOR flash power supply design

    Hi aruipksni, How do i calculate io current by rising/falling time and the output load ? Please help in this direction. Please share any document/link to read... Regards, Thulasi
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    Parallel NOR flash power supply design

    Dear Sir, I want to calculate the power requirement of an NOR flash from micron. IC requires two power supplies: VCC(core) & VCCQ(I/O). I calculated the power requirement of VCC(core) from the data sheet as VCC(max) * ICCW. I want to calculate the power requirement of the VCCQ(I/O) supply...
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    I2C Address in FPGA without external hardware pins ?

    Dear sir, Can I implement a I2C slave address in a FPGA as fixed ? Or do i need to use 3 hardware FPGA pins for address lines to implement a slave address ? I have seen I2C devices whose address is fixed and can't be changed. So, if I implement I2C slave address as fixed in FPGA (without A0...
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    i2c interface in SFP transceivers

    i2c switch in fpga Dear sir, We want to implement I2C switch (PCA9548A)in FPGA for our board design. How do we estimate the LEs required for the above functionality before writing code ? Or do we need to write code & then select the FPGA ? Has anybody implemented earlier, please help...
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    i2c interface in SFT transceivers

    Dear Sir, We would like connect I2C master to 8-I2C slaves(SFP Optical transceivers) which will not have I2C addresses to distinguish. Is it possible to implement I2C address encoding from the master inside FPGA to access each SFP transceivers's I2C internal space ? How about using I2C...
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    On Die Termination in DDR3

    Dear sir, I would like to know what is the purpose/use of On Die Termination control pin in DDR3 memory chip. When will it get asserted by controller (during read/write)? Can this pin be permanently pulled HIGH at DDR3 chip to enable On Die Termination ? Please answer my query..... Regards...
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    High capacity NAND(32GB) flash connection to a controller with less address lines

    Dear Sir, I would like to connect 32GB Nand flash memory device to a controller which has address lines A0-A22 which can address up to 8MB only. Please share any document which explains interfacing NAND to a processor/controller. Regards, Thulasi
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    precharge and refresh

    Dear Sir, When prechare & refresh is used ? What is difference between prechare all and precharge ? What is the differrence between refresh & auto refresh ? When this will be used...? Please share any document which details this terms. Regards, Thulasi
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    [SOLVED] DDR3 Row, column and bank Address multiplexing

    Dear sir, I have 4Gb x16 DDR3 chip. I want to connect this to a controller which doesn't support 4Gb x16 configuration. Is it possible to connect 4Gb x16 DDR3 chip to a controller in 2Gb x8 configuration as 2Gb x8 configuration is supported by the controller. I mean, I will connect only 8...
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    PCIe to SATA Controller

    I am looking for a PCIe to SATA controller chip. Apart from Marvell, Silicon Image, J Micron any other vendor(s) which make such chips. Regards, Thulasi
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    Timing loop problems in SyncE

    Dear Sir, I was reading about SyncE. Please read the following text .... "Some new Ethernet PHY devices provide a dedicated pin for the synchronization input. The advantage of this approach is that frequency input can be higher than 25MHz—higher clock frequencies usually have lower jitter. In...
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    Boundary scan functionality of JTAG for onboard Flash programming

    Hi, Also my observation is that, boundary scan flash programming requires that the FLASH memory’s address, data and control signals be directly connected to an 1149.1 compliant device so that device’s boundary register can be scanned during each FLASH write sequence. Is my observation correct...
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