tramu
Junior Member level 3
Dear Sir,
I was reading about SyncE. Please read the following text ....
"Some new Ethernet PHY devices provide a dedicated pin for the synchronization input. The
advantage of this approach is that frequency input can be higher than 25MHz—higher clock frequencies usually have lower jitter. In addition, this approach avoids any potential timing loop problems within the PHY device."
My queries are.....
1. What is meant my timing loop ?
2. Why it is a problem in Synchronous Ethernet ?
3. How do we avoid timing loop problem in Synchronous Ethernet PHY using a dedicated pin for the synchronization input at PHY ?
Please help by sharing views/links/documents to read.
Thanks for any words of wisdom....
Regards,
Thulasi
I was reading about SyncE. Please read the following text ....
"Some new Ethernet PHY devices provide a dedicated pin for the synchronization input. The
advantage of this approach is that frequency input can be higher than 25MHz—higher clock frequencies usually have lower jitter. In addition, this approach avoids any potential timing loop problems within the PHY device."
My queries are.....
1. What is meant my timing loop ?
2. Why it is a problem in Synchronous Ethernet ?
3. How do we avoid timing loop problem in Synchronous Ethernet PHY using a dedicated pin for the synchronization input at PHY ?
Please help by sharing views/links/documents to read.
Thanks for any words of wisdom....
Regards,
Thulasi
Last edited:
