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Hi
I have some questions on the soft start process:
when start up the external load is zero or any possible value?
in general method, the vref of error amp is ramp up slowly to implementate the soft start, my question is how slow should it be? 10us 100us or 1ms?
BTW should over current...
If my over protection circuit sense the current of PMOS is larger than the limitation and turn off the PMOS, when should it turn on again?
Next clock cyle? or until the voltage LX is fall to zero?
In error amp design for buck converter, why OTA can only use in open loop error while OP can used in close loop shown in the attachemt.
And the comparing ramp signal is from 0-Vpp or can be design as any vlow to vhigh?
Thanks
adc question papers
In "A 10-bit 400-MS/s 160-mW 0.13-m CMOS Dual-Channel Pipeline ADC Without Channel Mismatch Calibration"
the part III said that
On the other hand, the 3 dB frequency during the sampling phase is set to be about ln(2^(N-1)) larger than
during the amplifying phase since signal...
I think you may read a Ph.D dissertation first, and you do not need kown the idea completely. Then you must go to Lewis's classic paper(jssc92,jssc87) about pipelined stage. They will help you to understand the principle of digital corrention, you must refer others if you want know the principle...
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