Opamp AC characteristic for ADC applications

[moisiad]

Hi again

I have completed the design of a two stage folded cascode OPAMP with the following specs :
Vdd=1V , Gain=67db, UGB=300MHz, F3db=100K
The specific OPAMP will operate in an ADC with N=8bits and Fclk=60MHz

My question is the following :
According to Baker Book "CMOS , Mixed - Signal Circuit Design" pp.339
in order that the settling time be less than 1/Fckl, the UGB is defined by the equation UGB>0.22*(N+1)*Fckl. So in my case the UGB=300MHz satisfies this requirements.

However what about the F3db. Is there any relation to the settling time of the OPAMP. Because i have run some first simulations in transient analysis and the OPAMP seems to have very large setlling time beside that the above equation is valid for my case.

 

[gdhp]

i think the f-3db can determine the BG, so influnce the speed

 

[alvays]

Does UGB have relations to your capacitive load?

 

[totoro]

unit frequency is enough

 

[extraord]

the first pole is generated by the miller or nested compensation capacitors.
they do have great effects on settling time, in normal case, nested compensation has
a better settling time. because nested compensation do not generate RHZ which make gain margin larger.

 

[Chung-Yuan Chen]

I am sorry that I think the GBW of your amplifier is not enough. I think the specs. as following:

Gain>60db, UGB>1200MHz
(under the condition the amplifier is the type of claas A ,Fclk= 60MHz and β=½ ; the F-3db is not very important, the concern is its power gain bandwidth.)

 

[sutapanaki]

Why not think of it like this - the opamp has a certain ac characteristic, but in the circuit of the ADC it works in a feedback configuration. In this case the -3db freq of the opamp itself is not important. What is important is the -3db of the closed loop gain. If you use the opamp as a follower, then the UGBW is very important because it will be -3db frequency of the follower. Your amplifier has to settle fast for an ADC, which means less ringing. That also means you should take care of the second pole, because it will influence the phase margine and hence ringing for insufficient PM. You don't want to have also very large PM, close to 90deg, because then it is slow again. Best is about 72-76 deg.
Another thing is not to have pole-zero doublets, because they slow the the transient responce too.
And finally, the UGB affects the slew rate which is important when the amplifier works with large signals.

 

[moisiad]

Thank you all for your comments

Chung-Yuan-Chen can you please explain me how you have calculated the UGB you suggest. Because i come in a quite different result according my calculations.

Thanks

 

[Chung-Yuan Chen]

Hi, moisiad~
Time Constant(ζ)=1/βωt.
For settling to within some accuracy, the settling time need becomes approximately 5ζ within half of system clock(assums taht the duty cycle is 50%). That is just my rough concept.

 

[andy2000a]

Hi , moisiad
why need fast OP_Amp ? your opa using for
A/D comparator ? in fast A/D like flash ADC use
pre-amp + dynamic compartor , not use "OPA"

gernerally , OPA is very slow , and if you need high speed OPA must be use "large current" or large W/L .

 

[moisiad]

The ADC is a 1.5b stage pipelined architecture. I think that a fast OPA is mandatory.The fact is that for my case (Fclk=60MHz, T=16ns) the OPAMP must has a settling time at least 8ns (T/2). I really dont know this is feasible in 1V, or i am looking for an exotic circuit. In the second case i will have to examine an other architecture (perhaps Flash ADC)