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Yes, the restrictions are for the byte lanes. Although they appear similar, I length-matched data[7:0] to dqm0 and dqs0, and separately matched data[15:8] to dqm1 and dqs0. The address lines are matched to each other, and the clock was specified as being equal to the address lines, up to 1.6"...
You know, I was thinking exactly the same thing. There must be a complimentary set of memory modules whose pins are the upside-down mirror of one another. I've had my heart set on these MT chips because of their 1Gbit density, but what's the use if I can only use one??
Here's my next attempt...
Too bad. I worked hard on that layout!
I'll go back to the original strategy and try it again, but this time I'll route only one chip. I also think I can re-order the traces to eliminate one via from each line.
Once I've laid out the first one, I'll use the bottom two layers to daisy-chain the...
I spent quite a bit of time trying to get the autorouter to route even one chip, and it would usually give up before completing. Granted, it might have if I spent even more time with it, but at that point I gave up and decided to try my hand at this one more time.
This time, I used only one...
Frank,
This is what the design guide suggests for using two chips, one per chip select. All common lines are routed according to this diagram. One could infer from this design a T, but more likely a daisy chain. TL1 is the breakout from CPU to the first via. TL2B (don't ask me why B comes...
FvM,
Your insight helps me quite a bit.
To reduce design time, I leveraged portions of a reference design that happened to omit termination. The design guide for this chip additionally states that the drive levels are programmable, eliminating the need for external termination. I am also...
Routing two x16-wide chips has turned out to be more complex than I had hoped. I've taken a break before routing the remaining ratsnest to post this message.
I'm trying to wire up two DDR SDRAM chips, one per chip select on a PXA310 processor. These are x16-wide chips MT chips with 15 address...
alias symbol
Cadence has a logical "alias" symbol that permits one to use multiple names for the same physical net. There are numerous uses of this symbol in a design I am referencing, and I would like to retain the original schematic design.
For example, a particular pin that returns current...
pxa310 layout
This may be out in left field, but I'm going to give it a shot.
I am designing a PDA and have come to the part where I lay out my PCB. In the past, my electronic hobbyist experience has served me well, but this time I'm in way over my head. I could really use some help from...
Re: China? Not a chance
I believe there are a number of assembly and pcb fab houses in North America who perform work here in North America, but farm out large production jobs to China to realize scale of ecomony. I'm looking for just such a company right now. When I find it, I'll post the...
I'm working with 0.5mm and 0.4mm pitch BGAs with pitches that require 0.1mm laser-drilled in-pad microvias, < 4mil interconnect trace widths, stacked buried vias, etc. I would appreciate suggestions for companies that do high density interconnects of this nature, and with whom you've worked on...
Hi Everyone.
I'm presently designing in ESD/EMI protection ICs for all the interfaces I suspect may be subject to ESD and/or will be susceptible to noise, or contribute to noise propagation. The design is a simple PDA device contained by an ABS/PC shell with the following interfaces:
-...
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