torinwalker
Newbie level 6
Routing two x16-wide chips has turned out to be more complex than I had hoped. I've taken a break before routing the remaining ratsnest to post this message.
I'm trying to wire up two DDR SDRAM chips, one per chip select on a PXA310 processor. These are x16-wide chips MT chips with 15 address lines. If I use only one chip, the process is relatively easy, but I lose half of my memory. In this day and age, memory is everything. I can't afford to chop the memory in half to 128M by using only one chip. Well, actually, I can afford to, but I don't want to. It's like building a Mustang with a four-cylinder engine - looks great on the outside, but the test drive has you wanting for something with more power.
The processor design guide suggests a max 1.1" total trace length between chips, and also suggests a balanced T layout. It also suggests using the two top layers. It also suggests, and suggests, and suggests. This design is highly constrained.
What you see here is my first attempt to lay out the chips. The autorouter just made a big mess, which is why I'm doing it by hand. Perhaps that is the usual case, but this is my first modern design - I'll thank you to humour me with what I'm doing here.
The layout and pinouts, including the density of these chips (0.5mm) makes it difficult to break out and keep everything on two layers.
I'm interested in your opinions on how this could be done better. Yes, I am aware that the trace lengths in each byte lane have yet to be matched. I can also imagine that the extra vias may cause ringing. It kinda looks old school, doesn't it?
Would it be considered bad form at this point to introduce a third (and possibly fourth layer) to route address and control lines? Data would be on the top two layers, (ground is layer #3) and address, control, and clocks would be on layers 4 and 5.
Torin...
I'm trying to wire up two DDR SDRAM chips, one per chip select on a PXA310 processor. These are x16-wide chips MT chips with 15 address lines. If I use only one chip, the process is relatively easy, but I lose half of my memory. In this day and age, memory is everything. I can't afford to chop the memory in half to 128M by using only one chip. Well, actually, I can afford to, but I don't want to. It's like building a Mustang with a four-cylinder engine - looks great on the outside, but the test drive has you wanting for something with more power.
The processor design guide suggests a max 1.1" total trace length between chips, and also suggests a balanced T layout. It also suggests using the two top layers. It also suggests, and suggests, and suggests. This design is highly constrained.
What you see here is my first attempt to lay out the chips. The autorouter just made a big mess, which is why I'm doing it by hand. Perhaps that is the usual case, but this is my first modern design - I'll thank you to humour me with what I'm doing here.
The layout and pinouts, including the density of these chips (0.5mm) makes it difficult to break out and keep everything on two layers.
I'm interested in your opinions on how this could be done better. Yes, I am aware that the trace lengths in each byte lane have yet to be matched. I can also imagine that the extra vias may cause ringing. It kinda looks old school, doesn't it?
Would it be considered bad form at this point to introduce a third (and possibly fourth layer) to route address and control lines? Data would be on the top two layers, (ground is layer #3) and address, control, and clocks would be on layers 4 and 5.
Torin...