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Hello,
I am new to RF, can anyone suggest a quick tutorial on how to design a simple rf transmitter than can send digital signals at data rates of 50 - 100 kbps and operates up to 2-3 meters? Also this has to work in a free band or unlicesend frequency range.
If not any app notes on some...
Re: FPGA
FPGA's are programmable devices that can be programmed to do almost any type of hardware function available. You can have it function as a processor one time or if you want to reprogram it you can make it into a uart or other types of hardware functions. The only catch is normally...
NCSim help
Hello,
I am getting this error from NCSim when I try to load my design along with the sdf files and the libraries for post plcae and route simulation.
Illegal character in name passed to vpi_handle_by_name().
The following message was reported while SimVision was accessing design...
modelsim hold violation
I have tried simulating it without any timing constraints(no sdf) and it passes perfectly. I have also tried slowing down the only clock in the system and still gives me the same problem.
The same problem in ISE4.1i was solved with a service pack upgrade, I was thinking...
ise ignore timing constraints
I tried searching the Xilinx site but havent found any useful info. I did find an answer for a similar problem in 4.1i. I am running Xilinx STA and have yet to find any problems.
The sdf file that is generated by ise 5.1 seems to be the problem and although I did...
setup and hold time+xilinx
Thanks but modelsim won't even start to simulate due to this error. I will try to check the constraints file to see how I might be able to fix it.
xilinx hold violation
Hello,
I have synthesized, and run the translate, map, place and route for the virtexe fpga in ISE5.1i but when I try to simulate the netlist that ISE5.1i generates along with the sdf file I get these errors.
# Time: 1733 ps Iteration: 0 Instance...
yes, but it seems to hang and not stop when i run the compxlib
also, since xilinx ise 5.1 generates a new .v file for every step does that mean I have to create a new testbench for the new *.v file that ise generated for the post layout simulation?
Thanks
compexlib
Hello,
I am trying to run my testbench to do a simulation check after Xilinx has done place and route for the design. When it brings modelsim up and tries to simulate it gives errors such as:
# ** Error: (vsim-19) Failed to access library 'xilinxcorelib_ver' at "xilinxcorelib_ver"...
help on mos varactors
Hello everyone,
Does anyone have any good and specific documentation on mos varactors such as accumulation mode varactors and inversion mode varactors?
I am trying to compare the characteristics of using an active capacitor to a passive capacitor for creating a loop...
winio.dll 0x378
What address did you write the data values to anyway? EPP Mode has 8 registers.
Base address is for SPP Data
Base address + 1 is for SPP Status
Base address + 2 is for SPP Control
Base address + 3 is for EPP Address
Base address + 4 is for EPP Data
While the other registers...
Hello everyone,
I am trying to design a simple Analog IC PLL for a school project, can anyone suggest a place to start(i.e. ebooks to read, tutorials, etc.). I understand only the very basic elements of a PLL(i.e. PD, filter, VCO) and would like to get the actual details and implementation to...
Help with LEDs!!!!
Hi friends,
I need to find out how or where I can get the maximum rise and fall times for some specific LEDs. I got the datasheet from the manufacturer but they don't seem to have this info on the datasheet. I just want to know exactly how fast I can modulate the signal on...
Re: how to start fpga
Here is the schematic link for the parallel III cable for xilinx.
**broken link removed**
if it doesn't open, try this link
http://www.xilinx.com/support/programr/files/0380507.pdf
or if you're looking to just purchase a parallel III cable, www.avnet.com offers one...
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