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Recent content by tibusso

  1. T

    sndr enob in current steering cmos dac

    I have to measure DAC for Wireless communication. When I look for the way of the how to measure DAC, I found "very few people wrote down their DAC's SNDR in their Paper." Most of them only measured DAC's SFDR. In measuring the DAC, All I have to do is to measure the DAC's SFDR? why...
  2. T

    verilog a code for ideal ADC

    Thanks Syswip for reply! Spectre finds an error during SpectreHDL compile. There is a syntax error in this line: "localparam integer levels = 1<<`bits;" Sorry but I'm not an expert with verilog. Where can I find disciplines.vams file? Added after 5 hours 11 minutes: Ok. I solved the...
  3. T

    verilog a code for 8 bit ideal ADC

    Hi all, Can someone find the error in the following code? module top; wire in, clk, out; ideal_adc i1(in,clk,out); endmodule module ideal_adc(in,clk,out); input in,clk; output [0:adc_size-1] out; voltage in,clk,out; parameter integer adc_size = 8 from [1:inf); parameter real...
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    verilog a code for ideal ADC

    Hi all, I try to compile this code but there is an error in line 42: localparam integer levels = 1<<`bits; Can someone help me to solve the error? following there is the entire code. /* * N-bit Analog / Digital Converters * * Input range is from vmin to vmax. * * Version 1c, 10...
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    test DAC with an ideal ADC

    Hi all, I have to simulate an 6 bit 4 GSps current steering DAC in Virtouso Analog Design Environment. I need of an ideal 6 bit ADC to test the DAC. How can I do? Do you have an HDL code for this component? Or it is better to build the ADC with ideal elements? Thank you
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