verilog a code for ideal ADC

[tibusso]

Hi all,

I try to compile this code but there is an error in line 42:
localparam integer levels = 1<<`bits;

Can someone help me to solve the error? following there is the entire code.

/*
* N-bit Analog / Digital Converters
*
* Input range is from vmin to vmax.
*
* Version 1c, 10 February 2008
* Ken Kundert
*
* Downloaded from The Designer's Guide Community (www.designers-guide.org).
* Post any questions on www.designers-guide.org/Forum.
*
* This ADC is preferred over the version given in Listing 26 of Chapter 3
* of "The Designer's Guide to Verilog-AMS" by Kundert & Zinke.
*
* These versions were modified to work around limitations in the
* existing version of Spectre (6.1.1 May 2007). As such, they
* are less capable than the originals and should discarded
* once Spectre is fixed (though it has been 12 years ...).
*/
`define bits 8

`include "disciplines.vams"

// N-bit Analog to Digital Converter

module adc (out, in, clk);
// parameter integer bits = 8 from [1:24]; // resolution (bits)
parameter real vmin = 0.0; // minimum input voltage (V)
parameter real vmax = 1.0 from (vmin:inf); // maximum input voltage (V)
parameter real td = 0 from [0:inf); // delay from clock edge to output (s)
parameter real tt = 0 from [0:inf); // transition time of output (s)
parameter real vdd = 5; // voltage level of logic 1 (V)
parameter real vss = 0; // voltage level of logic 0 (V)
parameter real thresh = (vdd+vss)/2; // logic threshold level (V)
parameter integer dir = +1 from [-1:1] exclude 0;
// 1 for trigger on rising edge
// -1 for falling
localparam integer levels = 1<<`bits;
input in, clk;
output [`bits-1:0] out;
voltage in, clk;
voltage [`bits-1:0] out;
integer result;
genvar i;

analog begin
@(cross(V(clk)-thresh, dir) or initial_step) begin
result = levels*((V(in) - vmin))/(vmax - vmin);
if (result > levels-1)
result = levels-1;
else if (result < 0)
result = 0;
end

for (i=0; i<`bits; i=i+1)
V(out) <+ transition(result & (1<<i) ? vdd : vss, td, tt);
end
endmodule


Thank you

 

[Syswip]

What kind error do you have?
Could you also share the content of disciplines.vams file?

Bests,
Tiksan

 

[tibusso]

Thanks Syswip for reply!

Spectre finds an error during SpectreHDL compile. There is a syntax error in this line: "localparam integer levels = 1<<`bits;"

Sorry but I'm not an expert with verilog. Where can I find disciplines.vams file?

Added after 5 hours 11 minutes:

Ok. I solved the problem by using the Cadence ModelWriter component. I attach an interesting tutorial about this topic.