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Recent content by TheBorg

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    New Spartan 3 Board: Wrong ID Code retuned ?

    Hi Group I have developed my own Xilinx SPARTAN3-400 board but have a problem when trying to connected via JTAG to the FPGA, i am using the USB Cable from Xilinx but with out luck. There is only one FPGA in the chain, i have rechecked power sequencing, and recehecked the connection to the FPGA...
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    New Spartan 3 Board: Wrong ID Code retuned ?

    xilinx idcode wrong Hi Group I have developed my own Xilinx SPARTAN3-400 board but have a problem when trying to connected via JTAG to the FPGA, i am using the USB Cable from Xilinx but with out luck. There is only one FPGA in the chain, i have rechecked power sequencing, and recehecked the...
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    Shift register problem.

    Hi Group I am about designing an SIRCS decoder realized in FPGA via VHDL, but it seems, that i have a problem with a shift register. The code below is a modified version of what i am trying to implement, in the code below i am allways trying to put a logical one into the shift register, but...
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    Set/Clear SIGNAL from two processes ?

    I have tryied shared variebles but a get the same error here (Multiple sources), but how do a declare a protected shared variable ? Thanks alot in advance. Best regards René
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    Set/Clear SIGNAL from two processes ?

    Sorry for my bad english :-( What i need is a technique to write to the same SIGNAL / SHARED VARIABLE from two diffent processes (If you try in Xilinx you get Multiple source on xxxxxx), so i need a technique that i do the same for me ? Hope that was a better explanation. Best regards René
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    Set/Clear SIGNAL from two processes ?

    Hello I now that i cant write to a SIGNAL from to different processes, but i now need to set a SIGNAL from two processes how can i realize that ? (Some other technique) Thanks alot in advance. Best regards René
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    Olimex Wiggler Clone w. AT91RM9200

    wiggler clone buy Hi Group. Have anybody here in the group succedded to use the Olimex Wiggler Clone with the AT91RM9200 with openODC or Rowley Crossworks ? (Works fine with the SAM7 devices) Thanks alot in advance. Best regards The Borg
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    Nee link to Spartan 2 starter kit

    Re: Starterkit Spartan 2 Hello Salma Thanks alot for your help, it was just what i needed ;-) Best Regards The Borg
  9. T

    Nee link to Spartan 2 starter kit

    Hello Group Could some one in the group give link for a god starterkit for the Spartan 2 (If possible with some SRAM but not a must) ? Thanks in advance. Best regards TheBorg
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    Xilinx Spartan 2 vs. Spartan 3

    spartan ii vs spartan iii Hello Group. Could anybody explain me the main differences between the Spartan 2 and Spartan 3 ? Any input is very appreciated, and thanks in advance. Best regards TheBorg
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    XC9536 combinatorial logic (Chip select)

    Hello Can anybody tell me if it is nessesary to supply the XC9536, with a clock when i only wish to use the XC9536 to create chip select in an 8bit uP enveroment ? Than ks alot for your help in advance. Best regards René
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    INOUT example (XC95144XL)

    Thanks alot for you help, but i am afraid that i dont understand how to combine this knowlegde with the INOUT term, do you may or could you give a short example in VHDL on how to read write from a databus ? Im sorry asking for this kind of help but simply complete stucked on the issue. Thanks...
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    INOUT example (XC95144XL)

    Hi. I have for some days ago written a subject about using INOUT in a VHDL design, i all got a responce on putting the INOUT bus in 'Z' state before reading, but that i allready had done. I use the 'Generate Expected Simulation Results' the only two state a can put on is for now '1' and '0'...
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    Q: XC95144XL VHDL inout

    Hi Thanks for your answer, but it looks like i still have a quistion, i allready in the source for my example put 'zzzzzzzz' on the bus to change for read, but as i have u nderstood i allso have to do it in the testbench ? I use the 'Generate Expected Simulation Results' and i relly have...
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    Q: XC95144XL VHDL inout

    Hi. I have now for some time tried to use the WebPack simulator from Xilinx, i have defined a port as inout port (databus for a SRAM), there is no problems writing to the port, but i cant get it to work when trying to read from the port according the simulator. I have added the simple test...
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