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Recent content by terryssw

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    Function properties window problem in Cadence 5.033

    Some times the windows pop up out of the limit of your display. You can try to continuous open up the Move function windows, then you will see the windows go down each time you press "M' and then just go out of your monitor :)
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    Typical capacitance with .18 um technology

    typical capacitance value Typical value ranging from 50fF to 10pF if you want the cap to process the analog signal. Too small will create the problem of matching and noise, and too large have consump too much area. If you want some cap that is not for precision signal processing (e.g...
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    Whats the meaning of fn and id in MOSFET noise ?

    Noise Summary Do anyone know what's the meaning of "fn" and "id", which is related to the noise of MOSFET (model used: bsim3v3)? I have thinking that probably "fn" is the flicker noise and "id" is the thermal noise components. But I don't think there is so much flicker noise in the design (it...
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    question on diode load amplifier

    One of the main problem using diode load is the gain of the amplfiier will be sensitive to process variations, since Av =gm1/gm2. If a high precision gain is required, the diode load cannot be used.
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    Anyone designed a comparator with NMOS only

    I think you have difficulty to get 9bit resolution comparator if you don't use preamplifier.
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    How to synchronize clock signals in Hspice corner simulation

    Re: Hspice simulations You must have a reset control pin in your clock divider circuit so that all D-flipflops always has the initial states that under your control. Initial condition set by simulators is not trustable in such type of circuits. Another method is to use some kind of...
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    The use of the SS or FF in differential comparator and OTA

    Re: SS or FF You should consider all four cases in your simulations. The worst case corner will be the case that leads to the worst performance of your specs.
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    Is it possible to simulate DNL and INL for a 10-12bit ADC?

    Re: Simulate DNL and INL I suppose you are going to measure the DNL and INL of the ADC / DAC at transistor level. Many of this type of ADC (e.g. clocked pre-amp and latch in flash, SC-MDAC in pipelined ADC) needs clock to do the normal conversion and generate the code. If you don't apply the...
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    Is it possible to simulate DNL and INL for a 10-12bit ADC?

    Re: Simulate DNL and INL ?? Without the clock, how can your ADC / DAC works??
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    early effect voltage in current mirror

    I think it would be not much problems, since although you have more contact, you must have identical contact structure over every small resistors, and they could be well match (the overall resistance has increase, but people usually don't care absolute resistance. Your resistor ratio still not...
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    How pac analysis works in spectre??

    pxf spectre example I think it would be better to explain in the following few points: 1. There must be only one frequency conversion effect done by the combination of PSS+PAC. 2. In PSS, you define your periodic operating frequency fs, which is also your center of the reference sidebands and...
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    How pac analysis works in spectre??

    pac spectre If you needed to use PAC, your circuit must be driven by a large periodic stimuli (e.g. clock in SC circuit or LO in mixer), and your circuit must work under the influence of such periodic stimuli. That's is why you cannot use normal AC analysis, since your circuit does not work...
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    early effect voltage in current mirror

    Can you discuss more on how reliable should be, or how you can measure if the device give reliable current? Since larger unit devices will always produce more reliable current, but we always preferred smaller unit devices in terms of matching? Is there some explicit limit on the choice of unit...
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    Where do the harmonics come from in OpAmps?

    Re: Harmonics Yes, I agree nonlinearity will appear also in low-level signal, but I do not agree nonlinearity will appear in small-signal. Your concept and theory is correct, but you just using a "wrong definition" and "wrong word phase" to describe your theory. "small-signal" does not really...
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    How to do proper biasing?

    Suppose in your second stage you have NMOS common-source amp and PMOS current source load. Then your second stage biasing current is mainly controlled by the PMOS current source, and actually Vgs of the NMOS is determined by this current. However if the opamp is used as a feedback amplifier, the...

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