Typical capacitance with .18 um technology

[gunturikishore]

capacticance scaling with technology

Hi ,

Can anyone tell me the typical capacitance values tht can be used for on chip Analog Design with .18 um technnology.

I will be happy if any weblink will be provided for the same.

 

[Vamsi Mocherla]

mimcap matching

Typical values can only be few pF if there is a constraint on the chip area. If the Chip area is not a very big constraint, then you can go for all the caps you want to have. So, try and get an estimate on how much your active area is and then calculate how much area is left. Also, if you are designing filters or swit cap circuits, your caps have to be really accurate. Hence you will have to consider laying them out as smaller caps in parallel. This will increase the chip area further.

 

[gunturikishore]

0.18u cmos unit capacitance

Can you please be more specific abt the Uppper and Lower bound? I want to know specificaly the lower bound, that is the minimum value of the capacitance.

 

[Colbhaidh]

capacitance scaling with technology

Main foundries support a MIM capacitor at 1fF/um2 and a PIS capacitor at 4fF/um2.

 

[MLR67]

site:edaboard.com mos capacitor capacitance

You need to know the think oxyde ,to know this capacitance

 

[Vamsi Mocherla]

typical area capacitance values mos

Most CMOS processes support MiM caps for sure. they have a unit capacitance of 1fF/um2. Coming to the sizes of caps, you have to have an idea for what application you want to have and how much die area you have.

 

[andy2000a]

typical area capacitance

maybe you can give him some real value like
area fringe
---------------------------------------------
poly1 <-> thin oxide ? f /um^2 ?
M4 <-> M5 MiM cap ? f /um^2 ?

 

[Vamsi Mocherla]

cmos accumulation cap matching

Like I have told earlier, on the 0.25u and 0.18u processes we have, the Unit cap for M4<-->M5 MiM cap is about 1fF/um2

 

[terryssw]

typical capacitance value

Typical value ranging from 50fF to 10pF if you want the cap to process the analog signal. Too small will create the problem of matching and noise, and too large have consump too much area.

If you want some cap that is not for precision signal processing (e.g. compensation cap in opamp or decoupling cap), then you can use MOS as capacitance and the capacitance can reach 50 pF and even several hunderd pF for decoupling cap if you have area.

 

[flyankh]

dr.shanthi pavan

But MOS cap have a big problem,its value will change when the voltage on it changed.Sometimes it can destroy your design if you haven't think about it.


Regards

flyankh

 

[ambreesh]

typical on-chip capacitance

Dear flyankh,
If you are using a MOS cap, one always takes care that the channel is in place. Else the linearity of the CAp would be lost.

 

[gunturikishore]

Actually I need it in Analog Design for capacitive voltge divider network for which I need typically 50fF to 150f F. I think the answers above suit my requirement. Thanks a lot to all who gave good suggestions.

 

[flyankh]

Dear flyankh,
If you are using a MOS cap, one always takes care that the channel is in place. Else the linearity of the CAp would be lost.

So I think the MIM CAP is better,becuase it is always on the linearity.

Regards

flyankh

 

[ambreesh]

MIM cap is better nodoubt, put one can have poly-poly cap also.
The problem is area consumed by MIM cap. If I remember well Dr Shanthi Pavan from IIT Madras in his PhD work has talked on use of MOS capacitor in filter design. "HIGH FREQUENCY CONTINUOUS TIME FILTERS IN DIGITAL CMOS PROCESSES "
Following is abstract of it
"This dissertation investigates the design of high frequency continuous time filters in digital CMOS processes. A technique called ``constant-capacitance scaling'' has been proposed to make possible the realization of continuous time filters which are tunable over a very wide range, while dissipating low power and realizing very high pole frequencies. It is shown that filters designed using this technique are optimal with respect to noise, distortion and dynamic range. The architectures developed utilize MOS capacitors as the integrating elements. This enables the use of a fully digital CMOS process. By careful modeling, it has been shown that distortion generated in the inherently non-linear MOS capacitors is not of concern for a variety of applications. An accurate model developed for accumulation capacitors has been implemented in a general purpose circuit simulator.

In order to demonstrate the power of constant-capacitance scaling, a fourth order Butterworth filter has been designed and fabricated in a 0.25 micron digital CMOS process. This filter uses scaling techniques along with MOS accumulation capacitors and has a bandwidth which can be programmed from 60 MHz to 350 MHz. The measured dynamic range of the filter is 54 dB. In order to keep the response of the filter stable over process and temperature variations, a resistor-servo tuning technique which exploits the square law nature of the MOS transistor has been developed. This method is sufficient for filters with low quality factors.

For very high-quality filters, the simple tuning technique used in the test chip may not guarantee sufficient precision. A more accurate and complex method based on the behavior of a filter-comparator oscillator is proposed. This scheme converts a filter into an oscillator. Analytical relations for the behavior of the filter-comparator system have been developed and verified through a breadboard prototype. The amplitude and frequency of oscillation are measures of the center frequency and quality factor of a biquadratic section. The novelty of the filter tuning loop proposed is that it decouples center frequency and quality factor measurements."