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DAC segmentation
Segmentation of current steering DAC depends on :
1. area (can be estimated my calc no. of current cells)
2. power (what will be LSB,MSB etc current spec. for resolution)
3. matching (spl. lower than 130nm)
4.glitch energy--> critical in deciding upon segmentation.
5...
Vin is the reference means vout will be calculated with vin as ref. , vout/vin...
this simulation gives TOTAL noise w.r.t. Vin..
flicker noise is contained if you have evoked or changed the correct BSIM parameters of flicker noise.otherwise not.
DLL lock o/p switching
hi, i am simulating a DLL and it is suppose to lock at 800MHz.
the issue is after locking it again shows un-locking(digital o/p goes zero) but the frequency of the output nodes of various delay lines remains same (800MHz with .5MHz variation)
Can someone suggest what is...
how abt using in batchmode(non-GUI) and put '&' after command line..also set autologout for the server to the some days ...more than for which you expect your simulation to get over.
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Ur transistors are in Triode region and you need to define DC for your gate. before starting AC analysis DC operating pt. is established.
as someone rightly suggested, you need to increase Gate voltage of PMOS to reduce VDSAT and Increase Vds.
u get poor gain because the transistors are running...
M1 M2 ,i think, provides (with the help of Capacitor) a load which improves PSRR.
M17 as i see is switching ON the current mirror with the help of startup ckt..
M13 (1st ckt.) necessarily provides current to the ckt.
one is fourier transfor(.four)
and FFT=Fast Fourier Transform
so ,the result bwill be same..its just that the Alog. used to carry out fourier transform is different from FFT !
vdsat vds(sat)
I guess generally,they are v.close....
the problem is you need to get a point where your switching of liner to sat. is happening and accurate W/L for that may not be applicable in spice/layout.
Also vdsat doesn't always remain vgs-vth due to lamda effect..., it starts increasing...
opamp current source
In layout. the need is to match the MOS.
you have to take care that while designing you have to keep L same and W same with M factor of MOS variable. So in layout when you do fingering,each finger can have size of W or lower multiple of W.
Also orientation is important, but...
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