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Re: Regarding Offset Voltage
Thanks Djalli for your reply,
In the case of the pramplifier of Comparator, in that case which devices contribute more offset, input or load devices ?
Input devices are NMOS and Load devices are Diode connected(G&D connected) PMOS devices.
Thanks
Suraj
Regarding Offset Voltage
Dear Friends
I have questions related to the OFFSET voltage
1. Which is the main contributor of the OFFSET voltage of the differential amplifier, input devices or the load devices?
2. To reduce the OFFSET voltage when designing the circuit what aspect ratio do we...
Helo Hagen,
Use the input transistors aspect ration larger and load transistor aspect ratio smaller, to achive the less input referred noise.
Please go through with the Dr.Raazvi book, he has expalin the noise concept at circuit level very clearly.
Suraj
Re: about speed of compare
Hello,
I think there in no clock in your comparator.
In this case if you have a differential amplifier in first stage.
out put waveform's rise and fall time depends upon the output cap.,gain of the Diff. pair.
Gain also depends upon the gm, baised current, W/L. So...
Re: about speed of compare
Hello Friend,
I didn't get your question.Particularly last sentecnce, can you please explain in more detail, i can try .
Suraj
Re: noise reduction
Hello Friend,
Say we have a differentail amplifer. Input referred noise can be minimised by increasing the gm of the input transistor and at the same time reducing the gm of the load transistor.
Please correct me if I am wrong.
Suraj
Hi
You can study Offset volatge causes and effects and Noise issues and design circuits keeping in mind LOW VOLTAGE AND LOW POWER effects.
It is really challenging and rewarding.
Suraj
Re: Regarding Offset Volatge
Sir I don't have pictures.
This is related to the Differential amplifer given in Dr. Raazvi's book P 468- 470. In which input refeered offset volatge decreases with the decrease in (VGS- VTH), but current mismatch increases.
Suraj
Regarding Offset Volatge
Hello Friends,
If you we reduce the (VGS- VTH), then input offset referred offset voltage decreases but at the same time current mismatch increases. Can you please explain me this concept.
Suraj
Question about OP AMP
Hello Friends,
I have question about OP Amp:
In the Symbol we have two input terminals of the OP AMP (called positive and negative respectively). In the schematic we have two input transistors (say NMOS), then how we can say which transistor is held at positive and...
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