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Hello friends:
I am learning the hamming code recently, about the (7,4) type hamming code;
I try to understand the following :
M=(0 1 1 0); M is one of 16 possible messages;
G is the generate matrix;
X= M * G =
[0 1 1 0]
*
1 0 0 0 0 1 1 1
0 1 0 0 1 0 1 1
0 0 1 0 1 1 0 1
0 0 0...
hi,
agree with pavan,
Accordingly, in the manufacturing process, it has become difficult to form a via of a desired pattern. In a worst case scenario, an open failure occurs in the single-cut via formation part .
To reduce the manufacture failure chance.
there are so many, at each step of the chip design.
I think you should see books about chip Back-end/DFT/Reliability/ technology.
DFT is a tech for detecting and avoiding the chip product failure .
Hi,friend
Reading the veriligHDL book introducing the excution machenism about "=" and "<=" ;
From the software repect , how the VerilogHDL Compiler is working? decided by the Compiler itself.
For "=" :
Compiler excution start:
1st step : excute the b=a; time 0 -> 5(assume)
2nd step ...
Hi,qieda
3k.it should be helpful for understanding the reset issue.
---------- Post added at 10:56 ---------- Previous post was at 10:52 ----------
Hi,
maybe. These questions are basic, but so important.
soory.
had made a mistake there,
it is 2/3/4 8 bits adders separately. the result is 2 adders:9, 3:10, 4:10.
---------- Post added at 08:17 ---------- Previous post was at 07:56 ----------
Hi,
qieda
7 :::::: the system level or gate level just from the language architeture,eg, at...
HI,reading the follwoing ,maybe helpful for the test in the future.
2 : 1111_1111 + 1111_1111 = sum-width; 1111_1111 + 1111_1111 =？ 1111_1111 + 1111_1111 + 1111_1111 = ？
3: NO DONE TIME i think. just better,no best. U should try your best to find the debug of the system, even if it can...
i remember can setting using the ISE tool,configure the download mode, configure downloading sram connected serially :{sram(.sof)}-{sram.sof}-{sram.sof} .
Re: Amature in CAD tools
yeah, agree with phoenixpavan.
Go to Cadence/Synosyys CO. Net, register and download what you want.
en,,,,u had better do some samll labs;
Reading the blogs at the website maybe helpful,u can try.
Of couse , visit the edaboard , ask and talk helpful.
HI:
Post simulation (choose it at the ISE's menu option) is simulation after the physical mapping process, it will consider the realistic delay of the cell and net, but the fuction simulation is a ideal case.
Had you used ythe input port in your design(always/assign)? if u justly declare the...
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