Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
I am trying to get Xilinx microblaze to do the simple operation like output = input, I don't want to include UART port or any other similar port to it at this point. (Later on I want it to work with an external RAM)
This is how I tried to do it:
1- In ISE I did "project\new source" and chose...
Thank you for your help. I was wondering if you can provide more information on how you created and used the bus functional model. I am trying to make sure that I am in right path...
I googled it, I found a document from Xilinx that suggests using "Create/Import User Peripheral" (in XPS) to...
I am trying to use SystemVerilog with Active-HDL tools to verify a project that includes Xilinx microblaze soft core. The project includes a software (in C) that is developed in Xilinx SDK tool.
How can I include this software part (the code that is developed for microblaze in Xilinx SDK tool)...
I was wondering if there is any way to make LTSPICE to save average voltage values of all nodes to a file. I know you can get average voltage value of any node in the waveform window by keeping ctrl key down and clicking on the name of the node, but my circuit is very big. I hope there is a way...
I am dealing with a project that I need to compute the probability of failure for it. The system is made of different sub-systems. This is a digital system. I think the probability of failure of each sub-section should be related to the area occupied by that sub-system and also the activity rate...
I am trying to compute the probability of failure of the following system. "p" is the probability of failure. Note that system has two inputs and two outputs and some elements are shared between inputs.
Hi
I am trying to use ZBT Synchronous SRAM on the ml501 virtex 5 board. Where can I get a tutorial on how to use it. For example I can not connect the output and input pins of the FPGA to the input and output pins of ZBT. I need to know how to configure/identify the pins.
I am trying to use the USB port in my ml501 (vertex 5). I know how to send data through USB port, but I am not sure how to receive it. How can I identify USB ports in the USB drive on the board to connect FPGA to them.
I am trying to use virtex 5 (ml501) for a mpeg decoder that I have recently downloaded. The video is supposed to be sent to the FPGA through Ethernet port.
These are the signals that are supposed to be connected to Ethernet:
output [3:0] TX_DATA_P; // Ethernet transmission data...
I need the verilog code for Mpeg-2 decoder. I need all parts like iDCT core and a SDRAM to be separate. I searched the web, I could find some Mpeg-2 decoders, but the decoder was written in such a way that I could not separate the parts.
Verilog guestion
I have to modules:
module a(......, output reg f,.....)
always @(posedge clock) begin
.....
.....
.....
if (.....)
f=1;
else if (....)
f=0;
end
endmodule
module b(...., input f,.....)
a call(....,.f(f),...);
always @(posedge...
I am trying to use virtex 5 (ml501), It has a lot of input and output pins. I am using "planAhead" option to assign the pins, (in ISE). My problem is that on the board I can not find the corresponding pins, for example which pin is W13. I think it should have a data sheet explaining it, but I...
I am trying to make a simple FIFO buffer using verilog and ISE 10.1. I keep getting this warning for each bit of "_data_out" and the "_data_out" in RTL schematic is grounded.
WARNING:Xst:1710 - FF/Latch <_data_out_1> (without init value) has a constant value of 0 in block <in_north_0>. This...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
