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Recent content by sujithchakra

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    spartan 3e reset problem

    resetting spartan 3e Hi Tom, I am talking about the whole FPGA being reset in order to reload my design into FPGA again, not my design in the FPGA...I2C EEPROM(24XX256) does not have a reset pin on it.....here is the data sheet of EEPROM I am using...
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    spartan 3e reset problem

    spartan 3e reset Hi, My design has modules like i2c controller, cpu, sram, gpio. I integrated all the above modules. This design is implemented in Spartan 3e based Digilent Basys board. The design when triggered, reads data from the externally connected I2C EEPROM, copies into SRAM in the...
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    Problem in detection of Start and stop in I2C protocol

    Have look at the below site. It has free IPs of I2C EEPROMs. http://www.young-engineering.com/intellectual_property.html Hope this helps!
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    Xilinx XS - post- and pre-synthesis do not match

    Re: Synthesis Problems Hi, The problem is solved. I replaced 8'bx by 8'bz because there is nothing like 8'bx in hardware. Since 8'bx represents don'tcares, synthesis tool chooses some optimal value in place of 8'bx. Now my post synthesis simulation works fine. Thank you all for your suggestions.
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    Xilinx XS - post- and pre-synthesis do not match

    Re: Synthesis Thanks littlebu. Your suggestion helped me.
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    Xilinx XS - post- and pre-synthesis do not match

    Synthesis Problems Hi, I am using Xilinx XST to synthesize my design. Post-synthesis simulation is not matching pre-synthesis simulation. I figured out where the problem is. But I do not understand how to trouble shoot this. Below is one of the always block in my design. In pre-synthesis...
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    Xilinx UNISIM/SIMPRIM libraries

    xilinx unisim Hi, I am trying to do post-translate simulation on Xilinx ISE 10.1 on a PC(Win XP). When I try to compile the UNISIM/SIMPRIM libraries, the system asks for 3rd party simulators. So I installed Model Sim PE student edition. I am again stuck because my design is bigger than...
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    Timing delays - compiler directive delay_mode_zero

    Re: Timing delays Thank you for the reply rjainv. I shall try doing what you mentioned and see. Thanks, Sujith Chakra
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    Timing delays - compiler directive delay_mode_zero

    Re: Timing delays Thank you rjainv for the quick response. I did not understand "Take a design that meets design" in your reply. Can you be more clear? which simulator are you talking about? Is it Xilinx ISE? I am trying to simulate it using Xilinx ISE 10.1 to implement it in an FPGA. Please...
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    Timing delays - compiler directive delay_mode_zero

    delay_mode_zero Hi, I have a synthesized design(netlist) which I simulated using Cadence NC-Verilog using compiler directive +delay_mode_zero and functionality seemed to be correct. Now I am using Xilinx ISE to synthesize and simulate the design. I have two questions here. 1)How can I...
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    delay_mode_zero equivalent in Xilinx ISE

    Hi, Can any one please tell me what is the equivalent of "delay_mode_zero' compiler directive(Cadence Verilog-XL) equivalent in Xilinx ISE? Thanks, Sujith Chakra
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    Verilog and VHDL Synthesis

    Hi, Can someone tell me if we can synthesize Verilog and VHDL files together into a netlist in Verilog using Cadence PKS tool? Thanks, Sujith Chakra
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    Instantiation verilog

    Hi, I am writing a testbench for a bootup controller which controls a CPU and single port SRAM in verilog. The bootup controller first writes data into SRAM and then triggers Microcontroller to start reading data from SRAM. I have "address_boot" register in bootup controller which gives out the...
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    The differences between various I2C buses

    Could any one please explain the differences between.... 1) I2C bus core 2) I2C bus controller core 3) I2C master core 4) I2C slave core Thanks, Sujith Chakra
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    Array assignements in verilog

    verilog array slice Could any one please help me..... whats wrong in the following statements? reg [7:0] a [0:7]; a[1][0]<=1'b1; // I GET "SYNTAX ERROR" here when I try to assign "1" to element indexed [1][0] .I am using Cadence Verilog -...
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