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Recent content by student13

  1. S

    unipolar to bipolar conversion

    the attachment is in this post.
  2. S

    unipolar to bipolar conversion

    i have attached a diagram. in that i have the 2 currents (V phase and W phase) from IR2175 module which are unsigned and 12 bits. now i want to know how to convert these to the output of unipolar to bipolar module which are 12 bit signed. i think U phase current = -(V + W), but how to get V and...
  3. S

    unipolar to bipolar conversion

    Hello all, I want to convert digital uniploar signal to digital bipolar signal. for ex: 12 bit unsigned to 12 bit signed format. can anyone help me?
  4. S

    cordic code compression

    can anyone help me with documents or methods as to how to compress the following cordic code? actually it is using almost all of the resources, but i still have to implement many more blocks, hence the need for compression. module cordicnew(z0,x0,y0,xn,yn,clk); input signed [15:0]z0,x0,y0...
  5. S

    fixed point addition in verilog

    hello, i need to implement fixed point signed addition of 16 bits at every clock edge for CORDIC algorithm. but the very first addition is overflowing, can anyone tell me how to correct overflow or the method to work with fixed point with overflow. i am using 1 sign bit, 1 integer bit, 14...
  6. S

    resource requirement exceeds resource available

    thank you. so if i implement it using clock, how will i come to know of the number of clock cycles needed? and also how will i come to know about maximum freq clock can have? because all the operations have to be done in one clock cycle. please help me.
  7. S

    resource requirement exceeds resource available

    I got an error while trying to run CORDIC code which said: (device is spartan 3E XC3S100E) error1: Pack:2309 - Too many bonded comps of type "IBUF" found to fit this device. error2: Pack:18 - The design is too large for the given device and package. Please check the Design Summary section to...
  8. S

    using bram in verilog

    this is my main code. i have included functional model also. there it tells " You must compile the wrapper file bram.v when simulating the core, bram. When compiling the wrapper file, be sure to reference the XilinxCoreLib Verilog simulation library" what is a wrapper file and how to do...
  9. S

    fixed point division in verilog

    i wanted to implement fixed point format division in verilog. can anyone help me?
  10. S

    using bram in verilog

    thanks for the info, but I am still not able to use bram. can you just provide me with full examples such as the verilog code and full project. I have tried but still not sble to do it. sorry for asking such trivial things.
  11. S

    using bram in verilog

    Hello all, I am trying to implement cordic in verilog, and need to use bram. can anyone help me with some example code like initialization, storing and reading.
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