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Recent content by stevenv07

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    Implement IO power/ground and I/O signal PAD around digital macro

    Hello everyone, I have a problem as follows: My chip is analog hard macro dominant as shown in the attached figure. I/Os for analog hard macro have been implemented. The digital part is put at almost middle of the chip. It is difficult to place the I/O PAD for signals and power/ground at the IO...
  2. S

    [SOLVED] Power bump connects to power stripes

    Hello Oratie, In this case, there is no voltage supply protection. I mean if we apply a supply voltage over the nominal level to the bump, that voltage level applies to the standard cells directly. So, the standard cells may operate at high voltage level. Is there any risk in this case? Is...
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    [SOLVED] Power bump connects to power stripes

    Hello, I intend to connect the power bumps to power stripes directly. Can I do this? or I need to connect power bumps to power cells (placed at IO area), power cells are connected to the power stripes? Thanks so much. Steve
  4. S

    Overlap of block hard macro and flip-chip pad

    Thank you so much.
  5. S

    Overlap of block hard macro and flip-chip pad

    Hello everyone, In my design, I have an analog hard macro and its flip-chip pads. Their GDS and LEF files are separate. I implemented a block design with this macro, its flip-chip pads, and its controller in Cadence Innovus. Can I place this flip-chip pad over the hard macro in Innovus (see...
  6. S

    DFM for 28nm TSMC

    Thanks for your reply. Do we need to ask TSMC which DFM violations MUST be fixed and which CAN be ignored? Thanks, Steve.
  7. S

    DFM for 28nm TSMC

    Hello everyone, I checked the DFM rule after place and route, many errors happen such as RR:RE:EFP.Mx.S.5, RR:RE:EFP.Mx.S.6, RR:RE:EFP.Mx.S.7, etc. Some rules RR:RE:EFP.VIA1.EN.1, RR:RE:EFP.M1.EN1.1 even occur inside standard cells. What should I do in this case? How to fix them? Thanks in...
  8. S

    NLDM timing model for I/O cells

    Oh, I see. I can find it in the header of NLDM file. Thank you so much. Steve.
  9. S

    [SOLVED] ESD.18g DRC error in I/O cells

    Thank you so much. I just found it in the release note as you said. This DRC error can be waived. Steve.
  10. S

    NLDM timing model for I/O cells

    Hello everyone, When checking the propagation delay and transition time of I/O cells, its timing is provided in NLDM. But I don't understand how to look up the value in the table as shown in the attached image. Could you help me explain this? As I know, to look up the value in this table, we...
  11. S

    [SOLVED] ESD.18g DRC error in I/O cells

    I checked the document of TSMC IO cells, but there is no statements for waivers. Thanks, Steve
  12. S

    [SOLVED] ESD.18g DRC error in I/O cells

    Hello everyone, When I checked DRC for the whole chip (TSMC 28nm), two ESD drc errors happen (ESD.18g and ESD.19g). These errors relate to finger width of NMOS and PMOS in ESD circuits of I/Os. I don't know how to solve it. Could you please help me on this? The attached is the error description...
  13. S

    [SOLVED] Timing check at top level design

    Hello everyone, I have a digital block. I implemented it as a hard macro, and extracted the timing model .lib. Then, I instantiated this block into a top module (the top module only has this macro, and I/O pads), and do PnR. In the SDC file, I just set input and output delays associated with...
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    [SOLVED] Connect the core ESD power clamp to power mesh

    No, I did not use SROUTE command. I tried to edit powervia, and did not use blockpin option, then this issue has gone. Thanks. Steve.
  15. S

    [SOLVED] Connect the core ESD power clamp to power mesh

    I applied this command to the design, but Innovus did not connect all esd ports to the power mesh. Thanks, Steve.
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