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In analog design not difference betwen 0,5 or 0,6 in speed, noise and over factor. Its equivalent technology. You can choice fab and develop your circuits for it technology.
You must use verilog output format and load synthesized code in verilog (verilog netlist) in modelsim or over simulator. Also you can use VHDL netlist.
fpga equivalent transistor count
equivalent gate counting is not precision method. Main difference between FPGA and ASIC design - clock and power managment,
Many years ago, in 1960 - 1970 most popular was NOR. Only DTL and RTL logic - in this technologic basis NOR implementn more simple, then NAND.
In multriemmiter TTL NAND most simple. This basis very popular in 1970-1980/
In CMOS not differerence, but tradition. Therefore - NAND ;)
difference in the code written for fpga and cpld
for example Altera Apex consist of FPGA LUT based cells and macrocells like CPLD. CPLD better for control devices, small decoders, automatic control , etc. FPGA better for DSP aplications
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