how to relate ASIC gate and FPGA gate

[gck]

fpga asic gate count

How you will decide the whether given ASIC can be implemented in FPGA. ASIC people are using some terminology called equivalent gate(WHAT is THIS?)
and FPGA people are using system gate(WHAT IS THIS?).

Thank you

 

[MarcS]

fpga gate size

Most ASICs can be implemented with an FPGA. The typicall reasons why an ASIC might not be transferable to an FPGA are:
(a) the ASIC has significant analog content on the chip,
(b) the ASIC is very high performance, or
(c) the ASIC is extremely large (transistor count).

The real question is not whether it can be done as an FPGA or not, but which choice, overall, is cheaper. This can be a complex consideration, but the general principle is that FPGAs are cheaper to design, but have a higher unit cost. For example, it may cost you $0.5M to design the FPGA implementation and $4M to design the ASIC version. But the FPGA costs $20 per chip while the ASIC costs $5 per chip. So, if you are going to manufacture more than 230k chips, the ASIC is cheaper. For smaller volumes, the FPGA is cheaper. This is simplified, and other considerations also play an important role. For example, the ASIC will also take longer to design, and cannot be changed easily.

The result in the market has been that FPGA have taken over the low and mid-level ASIC designs. ASICs are usually mainly used for high-volume, high-performance chips (processors) and mixed analog/digital chips (wireless). There are even some very big FPGAs available today, but they are very expensive and the costs to design them are starting to approach the cost of designing an ASIC.

Your second question seems to relate to how the "size" of a chip is measured in gates or gate-equivalents. An FPGA has a fixed and pre-determined number of gates available on the chip, so you would think this is a good measure for size. But in fact "gates" is a very weak size metric. For example, does a flip-flop or a mux count the same as an inverter? On an ASIC it gets even harder: How many "gates" are there in a PLL or a power controller or a RAM? That is where the "gate-equivalent" metric comes in. The gate-equivalent metric attempts to normalize the "gate count" of different objects by estimating how the element compares to a number of 2-input-NANDs. For example, some marketing departments estimate a flip-flop to be equivalent to about 6 2-input-NANDs. Other companies say, no it is closer to 8 because ours have enable pins - You see this is largely a silly exercise.

I suspect that you are trying to compare the "size" of an ASIC to the advertised marketing "size" of an FPGA. These "gate count" numbers can only be very rough guides.

The true, accurate metrics are either:
(a) the number of transistors on the chip. This is a measure of how difficult it was to manufacture.
or (b) the number of placeable objects in the design (RAM= one object; FF= one object; inverter = one object). This is a measure of how hard it was to design.

Hope this helps

The

 

[ASIC_intl]

asic gates vs equivalent system gates

Since a FPGA cost $20 and an ASIC cost only $5. How for large volume like 230k can make ASIC profitable where FPGA not?

 

[MarcS]

fpga choice

Total FPGA cost = Design-cost + parts-cost = 0.5M + 20*number_of_parts

Total ASIC cost = Design-cost + parts-cost = 4M + 5*Number_of_parts


Tot FPGA cost = Tot ASIC cost at about 230k chips

 

[ASIC_intl]

total equivalent gate count for design transistor

but the cost here is the selling cost!

u have shown manufacturing cost to be same.

 

[MarcS]

asic gates

This analysis is very simplified, but the assumption is that the customer will pay the same for an ASIC or an FPGA implementation. The customer doesn't care how you did it as long as it works according to spec. So the revenue for selling x number of units is the same no matter which choice you make.

And since Profit = (Total revenue - Total cost) you will find that for <230k units sold your profit is higher with an FPGA. For >230k units sold your profit will be higher with ASIC implementation. At about 230k units your profit is the same with both.

 

[ASIC_intl]

fpga equivalent gate count

But u have already defined the cost of ASIC($5) and cost of FPGA ($20) to the customer as different. How can u claim it to be same now in your last solution.

 

[steshenko]

fpga equivalent transistor count

equivalent gate counting is not precision method. Main difference between FPGA and ASIC design - clock and power managment,

 

[Nir Dahan]

gate count transistor ratio nand

in ASIC it is relatively simple - you get an equivalent NAND gate count. But you also have to notice the ratio of combo to sequential logic. In most designs if you get more than 10:1 ratio (combo:sequential) then it is a sign you might want to introduce more memory elements in your system in order to pipeline or pre-decode stages and thus eliminate a lot of combo.

in FPGA the situation is more complicated, depending on an FPGA you have to realize what resources are still left for you, things like RAM blocks, available CLBs, fast routing resources etc.
since a lot of FPGAs have RAMs distributed anyways across the chip - good designers know how to use them (for example as big LUTs) instead of taking precious CLBs.

ND

https://asicdigitaldesign.wordpress.com/