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Hello Folks,
I am unable to calculate the FIFO depth, if the data is written to the FIFO with write clock continuously and read from the FIFO with respect to read clock continuously. Where, Write_frequency >= Read_frequency. Since the data written to the FIFO is continuous, I am unable to...
Dear Folks,
I am converting parallel to serial of 8 bit data using shift register.
Bu,the problem is, shift register is completely zero for all the clocks.
Please rectify.
module parallel_to_serial (clk, reset, data_in, data_out);
input clk;
input reset;
input [7:0] data_in...
Re: power management IC-twl6030
Smart Reflex is the TI power monitoring system (V/I regulator).
in PMIC, the smart reflex is used to monitor the voltage , current parameters and rise an alarm if the device goes out of the required value. Generally, input power rails are monitored by this...
Hey FvM,
Thanks for writing on this thread. regarding the multibyte transaction, I just wanted to know, whether reading sequence of 4 bytes will be followed continuously register address + offset or using Repeated read bit transcation.
The spec i2c spec (NXP) says about multibyte transmission...
Hi andre_teprom,
Well, thanks for replying back. I just wanted to clarify that, the master device you mentioned is FPGA. But I in my context it is some external processor which is I2C master. I would also like to ask you that, how can master device will read 32 bit data continuously or in four...
Hello folks,
I am communicating bw FPGA and a processor using I2C, where processor is a I2C master and FPGA is a slave.
I need to assign all the register width to 32 bit using 8 bit register address.
How to read/write data from register of size 32 bit wide.? I am using I2C slave which can be...
I am using spartan 3an for my application. I am using non volatile flash to store my bit stream and using Internal Master SPI Mode. During the configuration stage, some of the dual type I/O's has to be taken care as shown in UG332(217 page). I have connected the mode select pins m[2:0] to 011...
Hi all,
Hi all,
I am on the way to run linux on microblaze. I am stuck up with a problem from Device Tree Resource. I am using ML605 board.
I added the boot args and console device in the device tree specification window and then I pressed OK.
bootargs: console=ttyS0 root=/dev/ram ip=on...
Hi Reid,
I did the same thing when I saw it for the first time. I got a reply back saying,
Thank you for your HDL Designer evaluation request.
Your request is now being routed to our sales channel.
itseems, sales representatives will contact soon.
...Is there any other way I can try this...
Hey folks,
Can someone tell me how can I use the Mentor Graphics HDL Designer/Author tool for free?
Or
Is there any trail version available for some days?
Thank you.
Hi folks,
I am using spartan 3AN (XC3S50AN-4FTG256) for my design. How should I calculate the power required for running the design in FPGA.?
As per my understandings it requires,
VCCint = 1.2 V.
VCC (AUX) = 3.3 V
VCCO (Output supply Voltage)
GND
All pins need to be connected.
Is my...
Hi folks,
I am using ML605 (Vertex 6) Evaluation kit. I want to test my design output in oscilloscope. So, I am not finding any test points in the board.
I went through the data sheet and getting started guide related to ML605. But I am not finding any info regrading the same.
Please, can you...
Hi aruipksni,
Thanks for the reply. I got all your points mentioned. Can you please explain me in detail regarding the DUAL type and CLOCK type I/O's available?
Dual type I/O's are 40 in number. But how can I use them after configuration as general purpose. Regarding the clock pins, how are...
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