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Recent content by srihari_adem

  1. S

    confusion about generated clock when specify cts

    r u specifying the root clk as AutoCTSRootPin ? As far i know tools will not treat flop as through point by default ...
  2. S

    clock gating- problems

    might be you can try "set_clock_gating_check" to fix hold violations at synthesis stage for specified clock gating cells.
  3. S

    confusion about generated clock when specify cts

    If i understood correctly you are trying to build the CTS from pll_clk and this clk goes to divider (flops) and output of those divider will act as clock . Then 1.why r u building the CTS from root pin to this divider flop if there is no other sink to the root clock except divider flop. If...
  4. S

    clock gating- problems

    yes..no need to bother about hold violations because clock is ideal during synthesis (no CTS). All hold violations will get fixed in post route database.
  5. S

    Timing optimization of scan paths

    hold violations in scan will occur during shift phase where Q is connected to SI . Hold violations can also occur in capture phase where Q is connected to D without any combo. Remember same path can't cause both setup and hold violations to one endpoint. We can add a delay cell near SI to...
  6. S

    [SOLVED] Advantages of using clock inverters in CTS

    In general we will use inverters in clock tree to balance rise and fall delay mismatches. Essentially to maintain 50% duty cycle at CK pin of the flops. Especially when your logic operating on both edges like DDR.
  7. S

    clock gating- problems

    why r u bothering about hold violations at synthesis stage ? Clock gating hold violations can fixed like other hold violations during physical design phase. Techniques can used to fix hold violations are clock skewing/buffering in data path near to endpoint.
  8. S

    Do you check the recovery time and removal time ?

    Re: removal recovery time for a flip-flop yes you need to bother about recovery and removal checks for async resets. This checks are necessary for inactive state of reset to ensure unambiguous data was not captured by active clock edge.
  9. S

    VHDL Coding and Logic Synthesis with SYNOPSYS by Weng Fook Lee

    Re: need VHDL book Hi , That link is not working ..can u send alternative link Thanks Sri
  10. S

    How the delay is incorporated in Verilog synthesis?

    verilog Hi, I think synthesis tool will ignore the delays in RTL..Depends upon ur timing constraints the synthesis tool will pick up appropriate gates from library which accounts for delays. Thanks sri
  11. S

    What is the exact defination of clock skew related to digital/VLSI system?

    Re: Clock Skew difference in time between origin of clock and destination of clock where it needs to sample the data
  12. S

    need divide by 3 with 50% duty cycle circuit

    divide by 3 circuit hi all, can any body send how to design divide by 3 with 50% duty cycle. Is there any general method to design odd dividers with 50% duty cycle
  13. S

    NAND or NOR which is better preferred

    NAND always preferable in terms of logical effort and speed due parallel structure in pull up circuit.
  14. S

    PSpice reference guide

    iam uploading pspice ref manual
  15. S

    need materials for design compiler

    can anybody send related materials for synthesis using synopsys design compiler
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